Simulation Results: sram_ctrl/ret

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.40 %
  • code
  • 89.74 %
  • assert
  • 96.43 %
  • func
  • 97.03 %
  • line
  • 97.57 %
  • branch
  • 95.49 %
  • cond
  • 94.37 %
  • toggle
  • 89.85 %
  • FSM
  • 71.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1960.134us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.730s 37.600us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.850s 22.951us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.850s 474.350us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.499us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.800s 492.153us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.850s 22.951us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.499us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.770s 266.883us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.240s 203.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 265.480s 8318.948us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 150.850s 8709.151us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 53.370s 9493.858us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 433.750s 4765.356us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.490s 1823.799us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 107.180s 4718.870us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 8.530s 2292.831us 1 1 100.00
sram_ctrl_partial_access_b2b 333.450s 67283.241us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.940s 45.472us 1 1 100.00
sram_ctrl_throughput_w_partial_write 13.930s 181.230us 1 1 100.00
sram_ctrl_throughput_w_readback 14.170s 567.325us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 581.050s 35954.796us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.150s 78.861us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 667.490s 3913.722us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.640s 17.083us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.720s 456.529us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.720s 456.529us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.730s 37.600us 1 1 100.00
sram_ctrl_csr_rw 0.850s 22.951us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.499us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.890s 85.040us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.730s 37.600us 1 1 100.00
sram_ctrl_csr_rw 0.850s 22.951us 1 1 100.00
sram_ctrl_csr_aliasing 0.820s 14.499us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.890s 85.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.650s 395.678us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.450s 1908.871us 1 1 100.00
sram_ctrl_tl_intg_err 2.140s 309.684us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.450s 1908.871us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.140s 309.684us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 581.050s 35954.796us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 581.050s 35954.796us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.850s 22.951us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 107.180s 4718.870us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 107.180s 4718.870us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 107.180s 4718.870us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.490s 1823.799us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.400s 72.909us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.650s 395.678us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.230s 54.120us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1960.134us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1960.134us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 107.180s 4718.870us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.450s 1908.871us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.490s 1823.799us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.450s 1908.871us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.450s 1908.871us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1960.134us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.450s 1908.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 310.070s 2113.691us 1 1 100.00