Simulation Results: sysrst_ctrl

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.47 %
  • code
  • 91.10 %
  • assert
  • 90.23 %
  • func
  • 66.07 %
  • line
  • 96.19 %
  • branch
  • 96.77 %
  • cond
  • 93.29 %
  • toggle
  • 100.00 %
  • FSM
  • 69.23 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.770s 2115.128us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.120s 2449.877us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.690s 2424.154us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.410s 2323.977us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 5.040s 6081.975us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.830s 2276.475us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 116.710s 38907.654us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 7.540s 2610.413us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 5.320s 2084.755us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.830s 2276.475us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.540s 2610.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 218.190s 119511.346us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 202.730s 103181.161us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.570s 2899.527us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 6.220s 3737.245us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.220s 2522.009us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.010s 2178.545us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 5.000s 4672.138us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.960s 2630.569us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 1.710s 8312.683us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 37.650s 36758.415us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 29.140s 16081.012us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.790s 2015.301us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.020s 2155.282us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.510s 2119.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.510s 2119.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.040s 6081.975us 1 1 100.00
sysrst_ctrl_csr_rw 1.830s 2276.475us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.540s 2610.413us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.650s 5239.306us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.040s 6081.975us 1 1 100.00
sysrst_ctrl_csr_rw 1.830s 2276.475us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.540s 2610.413us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.650s 5239.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 73.970s 42012.137us 1 1 100.00
sysrst_ctrl_tl_intg_err 28.000s 42541.289us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 28.000s 42541.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.520s 12349.764us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
sysrst_ctrl_ultra_low_pwr 30039039215671568218849931620493269836701564549389436823704284776118131170077 659
UVM_ERROR @ 8312683094 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 8312683094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---