Simulation Results: uart

 
13/04/2026 19:14:24 DVSim: v1.30.1 sha: 4ae05e3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.90 %
  • code
  • 95.90 %
  • assert
  • 97.12 %
  • func
  • 49.69 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.45 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.570s 246.235us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.620s 14.738us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.780s 53.715us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.800s 252.632us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 96.271us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.900s 18.270us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.780s 53.715us 1 1 100.00
uart_csr_aliasing 0.720s 96.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 10.830s 19351.379us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.570s 246.235us 1 1 100.00
uart_tx_rx 10.830s 19351.379us 1 1 100.00
parity_error 2 2 100.00
uart_intr 8.770s 59308.003us 1 1 100.00
uart_rx_parity_err 14.510s 14313.629us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 10.830s 19351.379us 1 1 100.00
uart_intr 8.770s 59308.003us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 115.690s 97255.710us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 56.460s 50924.398us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 34.960s 56368.924us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 8.770s 59308.003us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 8.770s 59308.003us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 8.770s 59308.003us 1 1 100.00
perf 1 1 100.00
uart_perf 104.720s 11001.118us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.770s 4181.785us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.770s 4181.785us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 6.230s 16358.328us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.660s 6477.792us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.500s 222.368us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 32.090s 5388.545us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 566.720s 124055.205us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 205.180s 175073.791us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.620s 13.797us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.840s 46.019us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.370s 384.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.370s 384.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.620s 14.738us 1 1 100.00
uart_csr_rw 0.780s 53.715us 1 1 100.00
uart_csr_aliasing 0.720s 96.271us 1 1 100.00
uart_same_csr_outstanding 0.940s 52.550us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.620s 14.738us 1 1 100.00
uart_csr_rw 0.780s 53.715us 1 1 100.00
uart_csr_aliasing 0.720s 96.271us 1 1 100.00
uart_same_csr_outstanding 0.940s 52.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.910s 141.428us 1 1 100.00
uart_tl_intg_err 1.170s 156.788us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.170s 156.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 12.990s 8147.565us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 72598531982497149944897728247563060777711484258009399701637977332812839334824 75
UVM_ERROR @ 14690769399 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 14691115557 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 14691154019 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 14691192481 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata