Simulation Results: adc_ctrl

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 69.63 %
  • code
  • 95.77 %
  • assert
  • 95.62 %
  • func
  • 17.49 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 92.85 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 11.490s 5900.364us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.910s 791.590us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.000s 503.105us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 98.350s 43850.995us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.320s 916.614us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.150s 590.070us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.000s 503.105us 1 1 100.00
adc_ctrl_csr_aliasing 2.320s 916.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 196.270s 495020.654us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 833.710s 501086.959us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 301.510s 169257.137us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 272.380s 160920.531us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 220.890s 409446.455us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 312.970s 391413.110us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 31.210s 209687.084us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 65.520s 161356.371us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.780s 3046.200us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 60.820s 38556.547us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 52.750s 125857.416us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 22.360s 52983.072us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.500s 421.715us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.720s 319.745us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.080s 315.583us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.080s 315.583us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.910s 791.590us 1 1 100.00
adc_ctrl_csr_rw 1.000s 503.105us 1 1 100.00
adc_ctrl_csr_aliasing 2.320s 916.614us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.230s 4856.413us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.910s 791.590us 1 1 100.00
adc_ctrl_csr_rw 1.000s 503.105us 1 1 100.00
adc_ctrl_csr_aliasing 2.320s 916.614us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.230s 4856.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 14.810s 7880.145us 1 1 100.00
adc_ctrl_tl_intg_err 16.180s 8253.066us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 16.180s 8253.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.960s 23060.002us 1 1 100.00