Simulation Results: alert_handler

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.27 %
  • code
  • 90.95 %
  • assert
  • 98.05 %
  • func
  • 78.81 %
  • line
  • 99.64 %
  • branch
  • 97.92 %
  • cond
  • 90.36 %
  • toggle
  • 94.25 %
  • FSM
  • 72.58 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 18.280s 307.389us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.370s 70.578us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.110s 186.262us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 68.260s 1365.653us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 100.390s 15120.318us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.530s 108.311us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.110s 186.262us 1 1 100.00
alert_handler_csr_aliasing 100.390s 15120.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 45.200s 1174.166us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 34.730s 2020.213us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 462.790s 33091.335us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 16.260s 416.158us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 18.280s 307.389us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 2.570s 60.463us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 18.140s 335.659us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 69.500s 10528.078us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 904.270s 56731.888us 1 1 100.00
alert_handler_lpg_stub_clk 825.000s 53587.307us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1364.500s 129800.839us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 4.480s 229.935us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.970s 36.747us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.210s 17.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.680s 481.250us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.680s 481.250us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.370s 70.578us 1 1 100.00
alert_handler_csr_rw 4.110s 186.262us 1 1 100.00
alert_handler_csr_aliasing 100.390s 15120.318us 1 1 100.00
alert_handler_same_csr_outstanding 27.880s 3253.313us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.370s 70.578us 1 1 100.00
alert_handler_csr_rw 4.110s 186.262us 1 1 100.00
alert_handler_csr_aliasing 100.390s 15120.318us 1 1 100.00
alert_handler_same_csr_outstanding 27.880s 3253.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 93.430s 2333.180us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 93.430s 2333.180us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 93.430s 2333.180us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 93.430s 2333.180us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 206.070s 7901.239us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
alert_handler_tl_intg_err 5.930s 189.186us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 5.930s 189.186us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 93.430s 2333.180us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 18.280s 307.389us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 18.280s 307.389us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 18.280s 307.389us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 18.280s 307.389us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 16.260s 416.158us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 904.270s 56731.888us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 16.260s 416.158us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 462.790s 33091.335us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 462.790s 33091.335us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.280s 2189.915us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 12.080s 316.350us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 52840057279658477660490253872660770626961906174049779825384981471097923007818 93
UVM_INFO @ 10528078320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 5250398360955892172904257341699532572833066213065506670752328213920238436978 101
UVM_INFO @ 316349818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---