Simulation Results: chip

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.91 %
  • code
  • 85.00 %
  • assert
  • 97.25 %
  • func
  • 36.47 %
  • line
  • 94.35 %
  • branch
  • 93.68 %
  • cond
  • 88.63 %
  • toggle
  • 91.20 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
91.01%
V2S
50.00%
V3
65.38%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 167.030s 3317.658us 1 1 100.00
chip_sw_example_rom 78.390s 2008.772us 1 1 100.00
chip_sw_example_manufacturer 179.700s 3128.321us 1 1 100.00
chip_sw_example_concurrency 166.130s 2561.010us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 211.880s 5424.267us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 225.160s 4420.697us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2992.860s 43191.553us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4034.600s 34068.849us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 60.710s 2559.969us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4034.600s 34068.849us 1 1 100.00
chip_csr_rw 225.160s 4420.697us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.220s 42.161us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 266.790s 3580.706us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 266.790s 3580.706us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 266.790s 3580.706us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 393.420s 4031.144us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 393.420s 4031.144us 1 1 100.00
chip_sw_uart_tx_rx_idx1 377.040s 4441.207us 1 1 100.00
chip_sw_uart_tx_rx_idx2 353.150s 4390.799us 1 1 100.00
chip_sw_uart_tx_rx_idx3 330.890s 4140.120us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 343.630s 4145.278us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 323.300s 4054.520us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 602.010s 8229.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 219.710s 4607.434us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 219.710s 4607.434us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 187.910s 3222.391us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 149.840s 3364.704us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 198.970s 4257.500us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 910.400s 15134.090us 1 1 100.00
chip_tap_straps_testunlock0 440.980s 8896.522us 1 1 100.00
chip_tap_straps_rma 266.440s 5185.764us 1 1 100.00
chip_tap_straps_prod 406.470s 7662.316us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 208.650s 3603.069us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 818.540s 9405.081us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 471.200s 6466.226us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 471.200s 6466.226us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 550.910s 7727.142us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1143.190s 12185.484us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 424.860s 4353.184us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 507.420s 5821.672us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3414.470s 18878.442us 1 1 100.00
chip_sw_aes_enc_jitter_en 139.860s 2693.406us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 501.850s 6593.024us 1 1 100.00
chip_sw_hmac_enc_jitter_en 188.070s 3153.394us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1433.610s 12346.277us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 194.120s 3399.607us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 336.630s 4459.292us 1 1 100.00
chip_sw_clkmgr_jitter 136.750s 2532.775us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 203.560s 2946.711us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 157.700s 3205.315us 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 281.720s 5328.496us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 157.370s 2935.120us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 281.720s 5328.496us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 141.050s 2761.434us 1 1 100.00
chip_sw_aes_smoketest 170.440s 3386.986us 1 1 100.00
chip_sw_aon_timer_smoketest 234.390s 2993.977us 1 1 100.00
chip_sw_clkmgr_smoketest 129.420s 2697.242us 1 1 100.00
chip_sw_csrng_smoketest 193.940s 2844.245us 1 1 100.00
chip_sw_entropy_src_smoketest 811.560s 6958.947us 1 1 100.00
chip_sw_gpio_smoketest 226.000s 2821.049us 1 1 100.00
chip_sw_hmac_smoketest 166.890s 2942.755us 1 1 100.00
chip_sw_kmac_smoketest 190.170s 3468.907us 1 1 100.00
chip_sw_otbn_smoketest 920.330s 7350.071us 1 1 100.00
chip_sw_pwrmgr_smoketest 372.660s 7045.470us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 276.390s 6843.332us 1 1 100.00
chip_sw_rv_plic_smoketest 144.420s 2629.556us 1 1 100.00
chip_sw_rv_timer_smoketest 155.790s 3096.907us 1 1 100.00
chip_sw_rstmgr_smoketest 131.190s 3208.786us 1 1 100.00
chip_sw_sram_ctrl_smoketest 153.200s 2908.817us 1 1 100.00
chip_sw_uart_smoketest 156.930s 2392.233us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 122.410s 2597.080us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 340.630s 5831.591us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9058.310s 63833.216us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2881.020s 15828.660us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 140.290s 5929.623us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 244.270s 4009.625us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 228.560s 3263.548us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7670.950s 54956.860us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 8793.700s 58267.198us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 45.100s 2642.547us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 45.100s 2642.547us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4034.600s 34068.849us 1 1 100.00
chip_same_csr_outstanding 1517.360s 17473.728us 1 1 100.00
chip_csr_hw_reset 211.880s 5424.267us 1 1 100.00
chip_csr_rw 225.160s 4420.697us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4034.600s 34068.849us 1 1 100.00
chip_same_csr_outstanding 1517.360s 17473.728us 1 1 100.00
chip_csr_hw_reset 211.880s 5424.267us 1 1 100.00
chip_csr_rw 225.160s 4420.697us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 42.620s 1604.033us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 6.940s 39.243us 1 1 100.00
xbar_smoke_large_delays 53.960s 8528.838us 1 1 100.00
xbar_smoke_slow_rsp 46.570s 5131.102us 1 1 100.00
xbar_random_zero_delays 27.280s 458.093us 1 1 100.00
xbar_random_large_delays 41.760s 5906.338us 1 1 100.00
xbar_random_slow_rsp 248.100s 29479.229us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 6.480s 132.941us 1 1 100.00
xbar_error_and_unmapped_addr 32.410s 994.572us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 28.970s 1405.202us 1 1 100.00
xbar_error_and_unmapped_addr 32.410s 994.572us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 39.280s 701.987us 1 1 100.00
xbar_access_same_device_slow_rsp 176.420s 19292.109us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 11.810s 501.920us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 123.840s 5322.730us 1 1 100.00
xbar_stress_all_with_error 134.600s 5469.773us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 75.820s 365.775us 1 1 100.00
xbar_stress_all_with_reset_error 424.310s 14023.394us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2881.020s 15828.660us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2805.700s 29162.242us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2836.680s 15053.983us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2314.440s 11111.838us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2968.790s 15770.124us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2843.240s 15222.145us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2965.210s 15373.921us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2959.470s 15389.849us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2244.400s 11863.761us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3063.810s 19371.316us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3135.920s 15770.079us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3163.030s 17893.222us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 2784.870s 14938.341us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4121.230s 17693.325us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 5663.900s 24978.079us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 5435.680s 24397.383us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 5345.220s 24825.175us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5217.880s 24073.497us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4234.630s 17350.866us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 5207.070s 27490.315us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 5173.940s 24163.731us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 5202.120s 25006.909us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 4835.670s 22990.252us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2251.920s 11138.887us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 2934.060s 14576.162us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 2731.190s 15347.292us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 2769.710s 14424.448us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 2640.680s 14600.340us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2188.320s 10586.168us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3003.660s 17495.637us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 2998.680s 14816.243us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 2897.350s 16239.941us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 2696.060s 14258.615us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2284.520s 11665.595us 1 1 100.00
rom_e2e_asm_init_dev 3094.500s 15475.558us 1 1 100.00
rom_e2e_asm_init_prod 3114.240s 17232.162us 1 1 100.00
rom_e2e_asm_init_prod_end 3021.270s 17288.689us 1 1 100.00
rom_e2e_asm_init_rma 2765.030s 15144.044us 1 1 100.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5857.220s 28598.379us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5995.910s 29041.784us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5782.360s 28981.634us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3038.550s 16170.821us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3024.420s 34900.210us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3024.420s 34900.210us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 213.160s 3133.951us 1 1 100.00
chip_sw_aes_enc_jitter_en 139.860s 2693.406us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 132.500s 2871.266us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 188.840s 3291.422us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1048.960s 8819.848us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 145.410s 2753.799us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 377.640s 5778.003us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 375.080s 5251.372us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 567.000s 6186.401us 1 1 100.00
chip_plic_all_irqs_10 306.400s 3468.464us 1 1 100.00
chip_plic_all_irqs_20 409.630s 4274.090us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 169.410s 3696.687us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1040.560s 11018.045us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 327.550s 6199.472us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 143.000s 2620.873us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 827.690s 7137.818us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1108.190s 8733.402us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 800.700s 8525.759us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9688.390s 255872.977us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 310.000s 4534.692us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 372.660s 7045.470us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 310.000s 4534.692us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 388.760s 7020.842us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 388.760s 7020.842us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 257.830s 6841.641us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 352.060s 6076.642us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 526.720s 5473.659us 1 1 100.00
chip_sw_aes_idle 188.840s 3291.422us 1 1 100.00
chip_sw_hmac_enc_idle 197.810s 3084.086us 1 1 100.00
chip_sw_kmac_idle 185.600s 3304.220us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 318.690s 4649.203us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 272.320s 5042.842us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 256.690s 4675.296us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 306.420s 4534.594us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 829.250s 12198.110us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 418.540s 4415.948us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 359.850s 5161.555us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 354.930s 3414.948us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 408.740s 4571.143us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 374.920s 3887.175us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 402.220s 4552.760us 1 1 100.00
chip_sw_ast_clk_outputs 550.910s 7727.142us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 278.640s 6913.814us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 354.930s 3414.948us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 408.740s 4571.143us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 424.860s 4353.184us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 507.420s 5821.672us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3414.470s 18878.442us 1 1 100.00
chip_sw_aes_enc_jitter_en 139.860s 2693.406us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 501.850s 6593.024us 1 1 100.00
chip_sw_hmac_enc_jitter_en 188.070s 3153.394us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1433.610s 12346.277us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 194.120s 3399.607us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 336.630s 4459.292us 1 1 100.00
chip_sw_clkmgr_jitter 136.750s 2532.775us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 141.080s 2331.796us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 418.880s 4926.890us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 640.220s 7489.002us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3663.280s 24665.182us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 187.850s 3143.399us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 151.100s 3119.812us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1125.330s 11743.635us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 167.680s 2600.173us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 315.150s 4945.381us 1 1 100.00
chip_sw_flash_init_reduced_freq 1098.890s 21874.944us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4738.210s 37592.592us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 550.910s 7727.142us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 328.360s 4353.747us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 296.890s 3842.197us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 375.080s 5251.372us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 827.690s 7137.818us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1092.560s 8059.225us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 169.460s 2850.499us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 477.520s 6457.031us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 168.470s 3083.632us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3524.670s 20954.908us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 118.580s 2702.690us 1 1 100.00
chip_sw_edn_entropy_reqs 614.660s 6490.527us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 118.580s 2702.690us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1092.560s 8059.225us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 180.380s 3076.697us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 961.520s 15822.365us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 576.350s 6062.249us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 507.420s 5821.672us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 322.220s 4113.865us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 424.860s 4353.184us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3912.110s 44554.809us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 961.520s 15822.365us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 223.040s 3556.986us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1671.080s 13044.996us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.590s 2894.108us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3912.110s 44554.809us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.590s 2894.108us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.590s 2894.108us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.590s 2894.108us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 154.590s 2894.108us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 375.080s 5251.372us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 83.980s 4147.607us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 559.030s 4974.881us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 371.540s 5649.098us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 371.540s 5649.098us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 143.070s 2925.022us 1 1 100.00
chip_sw_hmac_enc_jitter_en 188.070s 3153.394us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 197.810s 3084.086us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1637.650s 10801.351us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 703.660s 5865.446us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 388.000s 4792.736us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 497.440s 5366.500us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 395.400s 4732.763us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 288.500s 3598.956us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1671.080s 13044.996us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1433.610s 12346.277us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1392.640s 11411.363us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1048.960s 8819.848us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2788.370s 14926.601us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 130.380s 3288.580us 1 1 100.00
chip_sw_kmac_mode_kmac 161.050s 2870.373us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 194.120s 3399.607us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1671.080s 13044.996us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 193.640s 3350.727us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1034.040s 8303.696us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 185.600s 3304.220us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 377.640s 5778.003us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 910.400s 15134.090us 1 1 100.00
chip_tap_straps_rma 266.440s 5185.764us 1 1 100.00
chip_tap_straps_prod 406.470s 7662.316us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 214.860s 3268.215us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1307.110s 10311.063us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 154.590s 2894.108us 0 1 0.00
chip_sw_flash_rma_unlocked 3912.110s 44554.809us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 243.860s 3479.634us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 448.260s 6279.225us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 473.950s 6495.754us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 505.460s 8052.181us 0 1 0.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_sw_keymgr_key_derivation 1671.080s 13044.996us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 318.770s 8884.174us 1 1 100.00
chip_sw_sram_ctrl_execution_main 566.640s 8429.630us 1 1 100.00
chip_prim_tl_access 83.980s 4147.607us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 278.640s 6913.814us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 418.540s 4415.948us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 359.850s 5161.555us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 354.930s 3414.948us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 408.740s 4571.143us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 374.920s 3887.175us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 402.220s 4552.760us 1 1 100.00
chip_tap_straps_dev 910.400s 15134.090us 1 1 100.00
chip_tap_straps_rma 266.440s 5185.764us 1 1 100.00
chip_tap_straps_prod 406.470s 7662.316us 1 1 100.00
chip_rv_dm_lc_disabled 71.890s 2351.158us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 189.110s 3500.583us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 87.690s 3547.719us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 71.870s 2713.924us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 81.430s 4095.250us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1680.880s 30874.170us 1 1 100.00
chip_rv_dm_lc_disabled 71.890s 2351.158us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 543.370s 8678.275us 0 1 0.00
chip_sw_lc_walkthrough_prod 645.820s 8174.313us 0 1 0.00
chip_sw_lc_walkthrough_prodend 566.930s 10336.710us 1 1 100.00
chip_sw_lc_walkthrough_rma 360.850s 5596.132us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1680.880s 30874.170us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 63.880s 2728.999us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 63.020s 2042.492us 1 1 100.00
rom_volatile_raw_unlock 47.220s 1882.697us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3527.040s 17208.678us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3414.470s 18878.442us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 526.720s 5473.659us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 526.720s 5473.659us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 526.720s 5473.659us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 307.030s 3439.272us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 961.520s 15822.365us 1 1 100.00
chip_sw_otbn_mem_scramble 307.030s 3439.272us 1 1 100.00
chip_sw_keymgr_key_derivation 1671.080s 13044.996us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 316.160s 5084.781us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 172.660s 2865.606us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 961.520s 15822.365us 1 1 100.00
chip_sw_otbn_mem_scramble 307.030s 3439.272us 1 1 100.00
chip_sw_keymgr_key_derivation 1671.080s 13044.996us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 316.160s 5084.781us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 172.660s 2865.606us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 276.850s 5366.308us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 214.860s 3268.215us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 243.860s 3479.634us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 448.260s 6279.225us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 473.950s 6495.754us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 505.460s 8052.181us 0 1 0.00
chip_sw_lc_ctrl_transition 586.580s 11555.821us 1 1 100.00
chip_prim_tl_access 83.980s 4147.607us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 83.980s 4147.607us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 738.600s 6905.644us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 272.260s 8928.787us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1044.020s 26723.046us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 242.010s 7265.738us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 328.590s 7374.331us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 422.130s 6608.617us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 711.010s 20535.525us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 180.420s 5551.730us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 388.760s 7020.842us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 811.950s 10321.433us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 301.200s 4467.824us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 272.260s 8928.787us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 317.170s 5647.676us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 502.430s 9089.928us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 283.370s 6454.568us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 296.300s 5004.421us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 229.450s 6224.992us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 617.470s 6993.687us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 859.660s 10017.375us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2007.890s 34147.103us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 153.120s 2602.450us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 375.080s 5251.372us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 318.770s 8884.174us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 318.770s 8884.174us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 859.660s 10017.375us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 229.450s 6224.992us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 301.200s 4467.824us 1 1 100.00
chip_sw_pwrmgr_smoketest 372.660s 7045.470us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 333.280s 3812.180us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 324.140s 5329.347us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 296.140s 4890.325us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1040.560s 11018.045us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 151.720s 3120.183us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 375.080s 5251.372us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1108.190s 8733.402us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 477.480s 4378.322us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 514.800s 5279.436us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 191.310s 3140.536us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 172.660s 2865.606us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 324.140s 5329.347us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 324.140s 5329.347us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1023.920s 13126.632us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 766.810s 13053.792us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 333.280s 3812.180us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 171.080s 2996.400us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 341.220s 7237.054us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 266.440s 5185.764us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 71.890s 2351.158us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 567.000s 6186.401us 1 1 100.00
chip_plic_all_irqs_10 306.400s 3468.464us 1 1 100.00
chip_plic_all_irqs_20 409.630s 4274.090us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 146.040s 2695.947us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 168.190s 3385.322us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2881.020s 15828.660us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 482.700s 7127.123us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 205.920s 3512.877us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 184.720s 3813.561us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 190.790s 2687.375us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 316.160s 5084.781us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 336.630s 4459.292us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 335.580s 7147.005us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 393.820s 8565.128us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 566.640s 8429.630us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 375.080s 5251.372us 1 1 100.00
chip_sw_data_integrity_escalation 471.200s 6466.226us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 617.470s 6993.687us 1 1 100.00
chip_sw_sysrst_ctrl_reset 934.100s 23250.774us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 184.970s 3319.442us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 216.100s 4295.968us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 336.680s 4977.431us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 934.100s 23250.774us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 934.100s 23250.774us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2384.290s 20647.758us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2384.290s 20647.758us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 353.690s 7408.057us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3024.420s 34900.210us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 153.830s 3029.598us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 159.280s 2808.568us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 246.010s 3564.150us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 336.090s 4431.966us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 989.750s 7788.164us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5618.670s 31598.220us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1864.740s 12604.667us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 164.210s 3237.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 169.900s 2589.586us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 87.540s 1895.137us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 11187.050s 72008.850us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1123.150s 6271.152us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 200.270s 4124.842us 0 1 0.00
rom_e2e_jtag_debug_dev 176.330s 4568.113us 0 1 0.00
rom_e2e_jtag_debug_rma 445.260s 6810.295us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 65.540s 2961.889us 0 1 0.00
rom_e2e_jtag_inject_dev 61.660s 2129.310us 0 1 0.00
rom_e2e_jtag_inject_rma 74.520s 1731.213us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 171.241s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 245.520s 3041.302us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 333.780s 3337.208us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 888.280s 5861.721us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 739.770s 6197.846us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 231.170s 2706.994us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 576.900s 5412.525us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 186.550s 2571.933us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 159.350s 3180.678us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 273.820s 6258.179us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 279.890s 4486.663us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 859.660s 10017.375us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 200.270s 4124.842us 0 1 0.00
rom_e2e_jtag_debug_dev 176.330s 4568.113us 0 1 0.00
rom_e2e_jtag_debug_rma 445.260s 6810.295us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 364.910s 6176.933us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 375.080s 5251.372us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5577.440s 38422.273us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5577.440s 38422.273us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 196.980s 3463.634us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 393.420s 4031.144us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3077.730s 19072.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
chip_sival_flash_info_access 180.740s 2834.015us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 402.080s 4593.605us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 7.860s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 160.230s 2872.281us 1 1 100.00
chip_sw_otp_ctrl_descrambling 174.490s 3299.581us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 281.830s 4055.761us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.363s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 187.740s 3223.932us 1 1 100.00
ate_bootstrap_flash_erase 6744.090s 45115.675us 1 1 100.00
ate_bootstrap_disjoint 9664.830s 84172.700us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 84177465903305655526853670381349192483268871289444912001880209277059084751988 320
UVM_INFO @ 3512.877309 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 112833691443837682365106650497926457732409338047191547826632916862018338530965 309
UVM_INFO @ 2894.107953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 80853672087408260946005869335184921666274941741141816506058098446530890071602 342
UVM_INFO @ 8052.181488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 59769860841592616672018259667929564760698162139249197585541046858798054644486 316
UVM_ERROR @ 3180.678068 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3180.678068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 55160255667232929971334634021185295108494433510753701565286096371762170555524 312
UVM_ERROR @ 2850.499450 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2850.499450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 105879868494761486028740883980920495806090397304816507916272555282106091103615 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 29814189480501644924868927260282057657123489429096532274008195453662133209729 369
UVM_INFO @ 8678.274928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 37082809012875186089866482665225779304476959075883674544027849718299333531982 369
UVM_INFO @ 8174.312666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 73355042250647796534598041019910841904036000400976546087489898295759499938899 341
UVM_INFO @ 5596.131699 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_sw_rstmgr_cpu_info 42671202943763036319249428157250296158954137639088434251040751532942517294255 333
TL item was: req: (cip_tl_seq_item@112471) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 5329.346904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_tl_errors 90881741654944796419321407079341865928529276507076656564573864445764601634713 217
TL item was: req: (cip_tl_seq_item@31451) { a_addr: 'h10490 a_data: 'hf75147da a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h181fb d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2642.547459 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 69458939728856189274781633945584881110636351000173589377355740455027137846275 224
TL item was: req: (cip_tl_seq_item@31805) { a_addr: 'h107e4 a_data: 'hed55c5f6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h1959a d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2559.968556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 95934024446588416951322313264153206552833769145948666599237050246609449878385 315
UVM_ERROR @ 6224.992000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6224.992000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 27746516850302687247137277431857702635921715912248758467875278743768854550540 314
UVM_ERROR @ 5551.730000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5551.730000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2819806405689288209287870080867305506813532940954010986973215182447107724521 328
UVM_ERROR @ 9089.928000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9089.928000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 93765298158828234188109065872465781859126691505739146185689868877240505029832 334
UVM_ERROR @ 23250.774500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23250.774500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 24556055209636289782230008315957979275225700146295322854053323440067162653212 319
UVM_ERROR @ 7020.842500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7020.842500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 103442413585361386338972097749482812830708639912472987742383593017772190208852 332
UVM_INFO @ 34900.210066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:382)] CHECK-fail: Expect alert *!
chip_sw_alert_test 97180907230654571041765835016804947356977743351195036857770575469472077691166 307
UVM_INFO @ 2753.798876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 35494055586455722485419398518087757099737097279518348213518495993740910836120 308
UVM_INFO @ 2620.872894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 106875430418685492843458659325956367454337603442225194812018055587309436849417 None
Offending '(reset_cause == HwReq)'
chip_sw_sensor_ctrl_alert 114811324818188529788758370053745393416973337591438080920344289726209430111395 316
UVM_ERROR @ 3205.314728 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 3205.314728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 115252084533454541518410884351002202792750543051770421659899651159699812468286 343
UVM_INFO @ 3041.301878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 79113227899465874298856814991436068731898305156695954896802678813025279084294 None
---- STDERR ----
Another command (pid=2293385) is running. Waiting for it to complete on the server (server_pid=270762)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 52137659636660066583415468850420321112863426444389291729755116278603813231332 None
Another command (pid=614256) is running. Waiting for it to complete on the server (server_pid=270762)...
Another command (pid=606629) is running. Waiting for it to complete on the server (server_pid=270762)...
Another command (pid=604001) is running. Waiting for it to complete on the server (server_pid=270762)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 79047487004489483034175336372683500126871479982884489184643146848966044511012 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 100322812814163303609532728360747048802322758558938644836227896343493582012330 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 8910303657286375721087726016258899858626005274302333013496016179072069417 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 27277018437140645629008633602709022053600979102834456582510283261421282430842 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 99655228507976387254675985258274830899633503873903639199773244471163692560309 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 66848478940921157022759338215235774981533762256309497470979582968717410761335 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 45209558859118048433487001063741412394269662039758649316618277468354709516857 215
UVM_INFO @ 2351.157854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 25064765906990421176883453429594158001869220653957765421172503087571760434936 331
UVM_INFO @ 1895.137392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 32576425837013614916220666984276933849082136988316691117454065808657764899032 312
UVM_INFO @ 4009.625000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 35854117845515851973514472794965595776536187831835130259860199980116741391953 318
UVM_INFO @ 3263.547500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 36035716900651716556495532900545440811748871899437334635172971073955414515330 327
UVM_INFO @ 12185.484476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_dev 89275580275349745150086724945244001986203923093061415786890318961797412000232 318
UVM_INFO @ 4568.112762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 45834095290695357957603932729556489328326201308096995138866052283180235131915 327
UVM_ERROR @ 5831.590740 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5831.590740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---