Simulation Results: clkmgr

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 98.66 %
  • assert
  • 95.62 %
  • func
  • 87.14 %
  • line
  • 99.30 %
  • branch
  • 99.15 %
  • cond
  • 94.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.100s 64.729us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.940s 29.645us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.170s 59.892us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.870s 214.215us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.630s 48.634us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.640s 44.645us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.170s 59.892us 1 1 100.00
clkmgr_csr_aliasing 1.630s 48.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.970s 24.240us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.060s 119.704us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.260s 67.562us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.190s 119.840us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.100s 64.729us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 3.920s 1095.144us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 4.960s 1044.951us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 3.920s 1095.144us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 12.140s 3922.759us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.180s 104.349us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.830s 187.914us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.830s 187.914us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.940s 29.645us 1 1 100.00
clkmgr_csr_rw 1.170s 59.892us 1 1 100.00
clkmgr_csr_aliasing 1.630s 48.634us 1 1 100.00
clkmgr_same_csr_outstanding 1.170s 66.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.940s 29.645us 1 1 100.00
clkmgr_csr_rw 1.170s 59.892us 1 1 100.00
clkmgr_csr_aliasing 1.630s 48.634us 1 1 100.00
clkmgr_same_csr_outstanding 1.170s 66.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 3.710s 1099.267us 1 1 100.00
clkmgr_tl_intg_err 2.130s 144.958us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.010s 135.556us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.010s 135.556us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.010s 135.556us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.010s 135.556us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.730s 540.240us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.130s 144.958us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 3.920s 1095.144us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 4.960s 1044.951us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.010s 135.556us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.200s 24.683us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.900s 73.202us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.160s 21.989us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.190s 31.107us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.070s 29.581us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.170s 59.892us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.710s 1099.267us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.170s 59.892us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.170s 59.892us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.710s 1099.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.670s 1015.951us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 51.120s 21551.014us 1 1 100.00