Simulation Results: csrng

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.27 %
  • code
  • 92.22 %
  • assert
  • 93.23 %
  • func
  • 79.37 %
  • block
  • 96.91 %
  • line
  • 97.62 %
  • branch
  • 92.25 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 24.169us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 27.000s 54.334us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 27.000s 23.919us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 54.000s 2077.384us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 29.000s 139.295us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 27.000s 17.177us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 27.000s 23.919us 1 1 100.00
csrng_csr_aliasing 29.000s 139.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
alerts 1 1 100.00
csrng_alert 36.000s 513.655us 1 1 100.00
err 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 28.000s 55.457us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 28.000s 55.457us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 1083.000s 63912.216us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 20.000s 178.062us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 27.000s 32.032us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 9.000s 736.005us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 9.000s 736.005us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 27.000s 54.334us 1 1 100.00
csrng_csr_rw 27.000s 23.919us 1 1 100.00
csrng_csr_aliasing 29.000s 139.295us 1 1 100.00
csrng_same_csr_outstanding 4.000s 128.265us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 27.000s 54.334us 1 1 100.00
csrng_csr_rw 27.000s 23.919us 1 1 100.00
csrng_csr_aliasing 29.000s 139.295us 1 1 100.00
csrng_same_csr_outstanding 4.000s 128.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
csrng_tl_intg_err 3.000s 105.898us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 32.775us 1 1 100.00
csrng_csr_rw 27.000s 23.919us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 36.000s 513.655us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 1083.000s 63912.216us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 36.000s 513.655us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 1083.000s 63912.216us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 36.000s 513.655us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 105.898us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
csrng_sec_cm 5.000s 117.432us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 23.000s 234.394us 1 1 100.00
csrng_err 23.000s 59.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 103966459853334286382075346664816375317981736786026187937720768518268543452805 130
UVM_INFO @ 55456995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
csrng_stress_all_with_rand_reset 104153749029625335044414983947888503812230475526396476596370702071600312815968 None