Simulation Results: edn/edn0

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.51 %
  • code
  • 79.20 %
  • assert
  • 94.36 %
  • func
  • 79.96 %
  • line
  • 96.79 %
  • branch
  • 88.42 %
  • cond
  • 83.81 %
  • toggle
  • 75.39 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.940s 50.974us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.840s 27.670us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.960s 28.144us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.790s 139.245us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 201.971us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.230s 93.186us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.960s 28.144us 1 1 100.00
edn_csr_aliasing 1.120s 201.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.170s 30.431us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.170s 30.431us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.170s 30.431us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 27.015us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.280s 45.812us 1 1 100.00
errs 1 1 100.00
edn_err 1.020s 22.141us 1 1 100.00
disable 2 2 100.00
edn_disable 1.050s 12.859us 1 1 100.00
edn_disable_auto_req_mode 0.970s 44.935us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.040s 323.750us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 16.232us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.040s 26.769us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.170s 42.308us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.170s 42.308us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.840s 27.670us 1 1 100.00
edn_csr_rw 0.960s 28.144us 1 1 100.00
edn_csr_aliasing 1.120s 201.971us 1 1 100.00
edn_same_csr_outstanding 0.890s 48.174us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.840s 27.670us 1 1 100.00
edn_csr_rw 0.960s 28.144us 1 1 100.00
edn_csr_aliasing 1.120s 201.971us 1 1 100.00
edn_same_csr_outstanding 0.890s 48.174us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.210s 559.885us 1 1 100.00
edn_tl_intg_err 1.450s 95.887us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 53.706us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.280s 45.812us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.210s 559.885us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.210s 559.885us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.210s 559.885us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.210s 559.885us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.280s 45.812us 1 1 100.00
edn_sec_cm 7.210s 559.885us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.280s 45.812us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.450s 95.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 79.070s 49989.319us 1 1 100.00