Simulation Results: edn/edn1

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.41 %
  • code
  • 83.93 %
  • assert
  • 97.14 %
  • func
  • 78.15 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 90.00 %
  • toggle
  • 94.80 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.980s 17.618us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 12.246us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 15.394us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.440s 65.466us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.010s 37.350us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.950s 22.716us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 15.394us 1 1 100.00
edn_csr_aliasing 1.010s 37.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.050s 54.959us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.050s 54.959us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.050s 54.959us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.870s 92.523us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.960s 25.889us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 57.789us 1 1 100.00
disable 1 2 50.00
edn_disable 0.830s 29.930us 1 1 100.00
edn_disable_auto_req_mode 1.080s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 1.220s 180.859us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.810s 43.009us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.710s 141.474us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.510s 79.015us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.510s 79.015us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.740s 12.246us 1 1 100.00
edn_csr_rw 0.800s 15.394us 1 1 100.00
edn_csr_aliasing 1.010s 37.350us 1 1 100.00
edn_same_csr_outstanding 0.880s 146.118us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.740s 12.246us 1 1 100.00
edn_csr_rw 0.800s 15.394us 1 1 100.00
edn_csr_aliasing 1.010s 37.350us 1 1 100.00
edn_same_csr_outstanding 0.880s 146.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.080s 362.961us 1 1 100.00
edn_tl_intg_err 1.320s 100.342us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 47.019us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.960s 25.889us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.080s 362.961us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.080s 362.961us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.080s 362.961us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.080s 362.961us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.960s 25.889us 1 1 100.00
edn_sec_cm 4.080s 362.961us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.960s 25.889us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.320s 100.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 35.240s 20860.635us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 28803946022356520999577011593730648512711328352470508542551730624072268047469 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---