Simulation Results: flash_ctrl

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.29 %
  • code
  • 93.85 %
  • assert
  • 96.67 %
  • func
  • 95.36 %
  • line
  • 96.01 %
  • branch
  • 97.06 %
  • cond
  • 93.50 %
  • toggle
  • 97.64 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 27.900s 22.258us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 14.480s 18.066us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 19.260s 47.388us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.030s 273.198us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 41.360s 638.013us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.350s 2130.903us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.070s 143.437us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.030s 273.198us 1 1 100.00
flash_ctrl_csr_aliasing 22.350s 2130.903us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.190s 16.707us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.420s 56.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 18.110s 82.050us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 26.380s 166.305us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1125.660s 425323.119us 1 1 100.00
flash_ctrl_hw_rma_reset 571.420s 170186.324us 1 1 100.00
flash_ctrl_lcmgr_intg 10.340s 183.694us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1515.790s 277604.623us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 129.710s 2063.170us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.690s 45.779us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1896.970s 312987.447us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 41.280s 83.004us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.380s 74.229us 1 1 100.00
flash_ctrl_rw_evict_all_en 18.040s 31.616us 1 1 100.00
flash_ctrl_re_evict 16.490s 79.688us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 46.580s 134.765us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 46.580s 134.765us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 193.610s 17678.275us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 18.980s 2313.556us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 135.960s 283.654us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 321.920s 6319.077us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 280.010s 790.958us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 744.650s 6103.439us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.830s 307.591us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 127.600s 3044.280us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 8.680s 28.077us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.930s 24.439us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 564.300s 1269.659us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 47.990s 2300.593us 1 1 100.00
flash_ctrl_otp_reset 50.160s 161.315us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1125.660s 425323.119us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 82.260s 2283.801us 1 1 100.00
flash_ctrl_intr_wr 50.020s 2798.578us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 176.280s 87584.235us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 128.390s 53335.846us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 50.520s 3347.991us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 38.130s 3718.628us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.710s 118.203us 1 1 100.00
flash_ctrl_ro_derr 117.510s 868.263us 1 1 100.00
flash_ctrl_rw_derr 139.900s 5417.603us 1 1 100.00
flash_ctrl_derr_detect 126.640s 4321.360us 1 1 100.00
flash_ctrl_integrity 456.280s 7748.577us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.760s 271.280us 1 1 100.00
flash_ctrl_ro_serr 88.120s 663.462us 1 1 100.00
flash_ctrl_rw_serr 125.660s 4294.041us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 30.570s 492.936us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 48.700s 3407.775us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 109.830s 4758.867us 1 1 100.00
flash_ctrl_write_word_sweep 6.760s 39.169us 1 1 100.00
flash_ctrl_read_word_sweep 11.890s 30.348us 1 1 100.00
flash_ctrl_ro 80.610s 619.677us 1 1 100.00
flash_ctrl_rw 383.660s 8089.338us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 27.660s 1381.030us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 582.410s 40299.596us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 43.360s 10034.009us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.890s 233.860us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.890s 56.413us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.430s 140.653us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.430s 140.653us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.260s 47.388us 1 1 100.00
flash_ctrl_csr_rw 8.030s 273.198us 1 1 100.00
flash_ctrl_csr_aliasing 22.350s 2130.903us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.770s 1450.417us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.260s 47.388us 1 1 100.00
flash_ctrl_csr_rw 8.030s 273.198us 1 1 100.00
flash_ctrl_csr_aliasing 22.350s 2130.903us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.770s 1450.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 15.300s 77.579us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 15.300s 77.579us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 15.300s 77.579us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 15.300s 77.579us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 55.360s 422.023us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
flash_ctrl_tl_intg_err 185.240s 826.316us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 185.240s 826.316us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 185.240s 826.316us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.000s 91.472us 1 1 100.00
flash_ctrl_wr_intg 6.710s 349.095us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 27.900s 22.258us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 50.160s 161.315us 1 1 100.00
flash_ctrl_disable 8.680s 28.077us 1 1 100.00
flash_ctrl_sec_info_access 50.800s 8703.815us 1 1 100.00
flash_ctrl_connect 6.930s 24.439us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.720s 23.226us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.030s 273.198us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 15.300s 77.579us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.030s 273.198us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 15.300s 77.579us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.030s 273.198us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 15.300s 77.579us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 8.680s 28.077us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.000s 91.472us 1 1 100.00
flash_ctrl_access_after_disable 5.810s 72.058us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.830s 52.337us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 8.680s 28.077us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 18.980s 2313.556us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 383.660s 8089.338us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 125.660s 4294.041us 1 1 100.00
flash_ctrl_rw_derr 139.900s 5417.603us 1 1 100.00
flash_ctrl_integrity 456.280s 7748.577us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1125.660s 425323.119us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.160s 887.561us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.260s 72.134us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 13.500s 697.638us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1622.350s 3557.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.490s 98.235us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 297.660s 765.362us 1 1 100.00