Simulation Results: hmac

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.13 %
  • code
  • 97.64 %
  • assert
  • 96.70 %
  • func
  • 43.05 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.39 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.120s 1632.562us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.920s 151.709us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.870s 19.365us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.590s 114.267us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.250s 428.049us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.330s 27.515us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.870s 19.365us 1 1 100.00
hmac_csr_aliasing 4.250s 428.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 14.070s 1005.302us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 62.660s 1463.132us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 174.960s 29764.896us 1 1 100.00
hmac_test_sha384_vectors 19.080s 428.605us 1 1 100.00
hmac_test_sha512_vectors 20.960s 229.831us 1 1 100.00
hmac_test_hmac256_vectors 9.820s 792.016us 1 1 100.00
hmac_test_hmac384_vectors 10.370s 616.036us 1 1 100.00
hmac_test_hmac512_vectors 10.050s 1287.084us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.830s 428.943us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 15.080s 447.988us 1 1 100.00
error 1 1 100.00
hmac_error 26.990s 1371.928us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 33.560s 9266.273us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.120s 1632.562us 1 1 100.00
hmac_long_msg 14.070s 1005.302us 1 1 100.00
hmac_back_pressure 62.660s 1463.132us 1 1 100.00
hmac_datapath_stress 15.080s 447.988us 1 1 100.00
hmac_burst_wr 5.830s 428.943us 1 1 100.00
hmac_stress_all 614.870s 104281.347us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.120s 1632.562us 1 1 100.00
hmac_long_msg 14.070s 1005.302us 1 1 100.00
hmac_back_pressure 62.660s 1463.132us 1 1 100.00
hmac_datapath_stress 15.080s 447.988us 1 1 100.00
hmac_wipe_secret 33.560s 9266.273us 1 1 100.00
hmac_test_sha256_vectors 174.960s 29764.896us 1 1 100.00
hmac_test_sha384_vectors 19.080s 428.605us 1 1 100.00
hmac_test_sha512_vectors 20.960s 229.831us 1 1 100.00
hmac_test_hmac256_vectors 9.820s 792.016us 1 1 100.00
hmac_test_hmac384_vectors 10.370s 616.036us 1 1 100.00
hmac_test_hmac512_vectors 10.050s 1287.084us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.120s 1632.562us 1 1 100.00
hmac_long_msg 14.070s 1005.302us 1 1 100.00
hmac_back_pressure 62.660s 1463.132us 1 1 100.00
hmac_datapath_stress 15.080s 447.988us 1 1 100.00
hmac_burst_wr 5.830s 428.943us 1 1 100.00
hmac_error 26.990s 1371.928us 1 1 100.00
hmac_wipe_secret 33.560s 9266.273us 1 1 100.00
hmac_test_sha256_vectors 174.960s 29764.896us 1 1 100.00
hmac_test_sha384_vectors 19.080s 428.605us 1 1 100.00
hmac_test_sha512_vectors 20.960s 229.831us 1 1 100.00
hmac_test_hmac256_vectors 9.820s 792.016us 1 1 100.00
hmac_test_hmac384_vectors 10.370s 616.036us 1 1 100.00
hmac_test_hmac512_vectors 10.050s 1287.084us 1 1 100.00
hmac_stress_all 614.870s 104281.347us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 614.870s 104281.347us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 14.192us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.610s 16.667us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.260s 208.201us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.260s 208.201us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.920s 151.709us 1 1 100.00
hmac_csr_rw 0.870s 19.365us 1 1 100.00
hmac_csr_aliasing 4.250s 428.049us 1 1 100.00
hmac_same_csr_outstanding 1.170s 152.598us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.920s 151.709us 1 1 100.00
hmac_csr_rw 0.870s 19.365us 1 1 100.00
hmac_csr_aliasing 4.250s 428.049us 1 1 100.00
hmac_same_csr_outstanding 1.170s 152.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.900s 95.821us 1 1 100.00
hmac_tl_intg_err 3.450s 1105.268us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.450s 1105.268us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.120s 1632.562us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.400s 131.973us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 83.350s 48839.222us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.810s 9.050us 1 1 100.00