Simulation Results

Simulation Results: i2c

14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.19 %

code
81.46 %

assert
96.19 %

func
77.91 %

line
96.38 %

branch
92.26 %

cond
85.16 %

toggle
89.45 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	31.000s	1008.881us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	5.950s	594.867us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.800s	31.256us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.770s	32.194us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.260s	236.547us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.490s	192.894us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.730s	72.290us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.770s	32.194us	1	1	100.00
	i2c_csr_aliasing	1.490s	192.894us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.840s	230.772us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	113.890s	6277.218us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	5.490s	520.694us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.770s	94.736us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	219.460s	19115.767us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	34.510s	3558.409us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.160s	226.838us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.860s	1075.002us	1	1	100.00
	i2c_host_fifo_reset_rx	7.100s	845.926us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	80.650s	1898.765us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	11.920s	1056.045us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	101.023us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.200s	1058.078us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	54.620s	42402.107us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.320s	1283.775us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	19.510s	1670.196us	1	1	100.00
	i2c_target_intr_smoke	4.490s	4901.220us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.960s	1439.818us	1	1	100.00
	i2c_target_fifo_reset_tx	0.920s	441.646us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	13.590s	32211.235us	1	1	100.00
	i2c_target_stress_rd	19.510s	1670.196us	1	1	100.00
	i2c_target_intr_stress_wr	360.850s	27592.242us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.040s	2495.672us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	10.580s	3241.562us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.660s	941.069us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.850s	1039.573us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.350s	333.280us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.520s	782.306us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	5.490s	520.694us	1	1	100.00
	i2c_host_perf_precise	1.210s	44.564us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	11.920s	1056.045us	1	1	100.00
target_mode_tx_stretch_ctrl				0	1	0.00
	i2c_target_tx_stretch_ctrl	0.880s	9.131us	0	1	0.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.920s	1760.182us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.830s	6748.607us	1	1	100.00
	i2c_target_nack_txstretch	1.280s	515.012us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.560s	719.843us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.960s	540.862us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.720s	47.869us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.790s	82.064us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.750s	168.536us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.750s	168.536us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	31.256us	1	1	100.00
	i2c_csr_rw	0.770s	32.194us	1	1	100.00
	i2c_csr_aliasing	1.490s	192.894us	1	1	100.00
	i2c_same_csr_outstanding	1.310s	107.252us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	31.256us	1	1	100.00
	i2c_csr_rw	0.770s	32.194us	1	1	100.00
	i2c_csr_aliasing	1.490s	192.894us	1	1	100.00
	i2c_same_csr_outstanding	1.310s	107.252us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.740s	484.416us	1	1	100.00
	i2c_sec_cm	0.920s	103.417us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.740s	484.416us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	26.430s	2514.094us	1
target_error_intr				1
	i2c_target_unexp_stop	1.270s	344.440us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	0.770s	48.153us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	81008674801068405336711830421853227399985218882840854822964492652552036134146	94	UVM_INFO @ 230771827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	70991811612041089543542453547599031163446859893102790009563961222250287280787	136	UVM_INFO @ 6277217894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	96912250603276536958638073945086994827925596780379736933215744428425294038152	85	UVM_INFO @ 48152738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	85847995311081021570670887259773141120567489470226517012365229790751840513167	84	UVM_INFO @ 1058078379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	78321231209390051950161052528663563891019636350608501356966037378578296757413	78	UVM_INFO @ 344439606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	60919569743989737390743095691595674976600910638735213405053204286864664119659	91	UVM_INFO @ 2514094088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access
	i2c_host_mode_toggle	85395508003101396305595172113810082071853681011819324154741428690927236603722	86	src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584 The object at dereference depth 0 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
Error-[CNST-CIF] Constraints inconsistency failure
	i2c_target_tx_stretch_ctrl	40807848328446337974029395324841749105893681636882464809322985371598639881336	130	src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872 Constraints are inconsistent and cannot be solved. Please check the inconsistent constraints being printed above and rewrite them.