Simulation Results: lc_ctrl/volatile_unlock_disabled

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.57 %
  • code
  • 83.82 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.08 %
  • branch
  • 93.67 %
  • cond
  • 78.95 %
  • toggle
  • 84.90 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.300s 116.660us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.410s 75.102us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.870s 151.852us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.790s 308.666us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 22.783us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.140s 90.157us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.870s 151.852us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 22.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.740s 47.575us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.970s 617.279us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.130s 30.779us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.630s 56.128us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.120s 410.086us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_prog_failure 2.630s 56.128us 1 1 100.00
lc_ctrl_errors 5.120s 410.086us 1 1 100.00
lc_ctrl_security_escalation 5.820s 1891.702us 1 1 100.00
lc_ctrl_jtag_state_failure 33.260s 5647.443us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.790s 1945.323us 1 1 100.00
lc_ctrl_jtag_errors 66.450s 3870.300us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 9.290s 6149.320us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.410s 542.521us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.790s 1945.323us 1 1 100.00
lc_ctrl_jtag_errors 66.450s 3870.300us 1 1 100.00
lc_ctrl_jtag_access 8.610s 462.273us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 19.180s 994.031us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.490s 182.301us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.470s 163.963us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.730s 344.033us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.590s 320.336us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.920s 130.713us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.140s 341.604us 1 1 100.00
lc_ctrl_jtag_alert_test 1.480s 33.129us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 13.100s 681.271us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.870s 14.455us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 54.850s 4365.560us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.060s 19.140us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 98.616us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.030s 98.616us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.410s 75.102us 1 1 100.00
lc_ctrl_csr_rw 0.870s 151.852us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 22.783us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.650s 192.093us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.410s 75.102us 1 1 100.00
lc_ctrl_csr_rw 0.870s 151.852us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 22.783us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.650s 192.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
lc_ctrl_tl_intg_err 1.560s 169.175us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.560s 169.175us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.970s 617.279us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.380s 280.629us 1 1 100.00
lc_ctrl_sec_cm 6.330s 251.166us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.820s 1891.702us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.740s 47.575us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.410s 542.521us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.880s 3472.966us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.880s 3472.966us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.560s 466.759us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 14.310s 769.357us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 14.310s 769.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 23.270s 5294.492us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 61149075317640499585668056460397654013566663054649194126433459459039346509545 7026
UVM_INFO @ 4365560133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 12694166425247731061322105457255293893128236266053233115629964706540309085358 1902
UVM_INFO @ 5294491523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---