Simulation Results: lc_ctrl/volatile_unlock_enabled

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.90 %
  • code
  • 83.22 %
  • assert
  • 94.13 %
  • func
  • 92.35 %
  • line
  • 97.10 %
  • branch
  • 93.62 %
  • cond
  • 79.42 %
  • toggle
  • 85.21 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.560s 35.949us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 16.753us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 14.393us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.310s 51.301us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 88.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.820s 35.709us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 14.393us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 88.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.040s 79.593us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.720s 841.624us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.810s 29.465us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.230s 99.323us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.790s 479.715us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_prog_failure 2.230s 99.323us 1 1 100.00
lc_ctrl_errors 3.790s 479.715us 1 1 100.00
lc_ctrl_security_escalation 3.760s 3949.578us 1 1 100.00
lc_ctrl_jtag_state_failure 40.540s 3799.032us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.770s 1362.020us 1 1 100.00
lc_ctrl_jtag_errors 21.810s 4377.061us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.620s 1668.579us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.820s 378.456us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.770s 1362.020us 1 1 100.00
lc_ctrl_jtag_errors 21.810s 4377.061us 1 1 100.00
lc_ctrl_jtag_access 3.440s 795.863us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.970s 5356.597us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.210s 588.839us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.690s 406.486us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 30.680s 4096.900us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.950s 1412.630us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.160s 49.539us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.100s 101.014us 1 1 100.00
lc_ctrl_jtag_alert_test 0.720s 57.825us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.230s 253.658us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 34.976us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 22.340s 1735.419us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.770s 19.745us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.370s 107.833us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.370s 107.833us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 16.753us 1 1 100.00
lc_ctrl_csr_rw 0.830s 14.393us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 88.084us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 17.934us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 16.753us 1 1 100.00
lc_ctrl_csr_rw 0.830s 14.393us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 88.084us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 17.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 219.929us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 219.929us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.720s 841.624us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.940s 260.498us 1 1 100.00
lc_ctrl_sec_cm 6.730s 138.841us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.760s 3949.578us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.040s 79.593us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.820s 378.456us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.330s 1456.784us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.330s 1456.784us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.020s 2295.132us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.230s 439.825us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.230s 439.825us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 36.280s 9813.083us 1 1 100.00