Simulation Results: otbn

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.90 %
  • code
  • 95.16 %
  • assert
  • 89.50 %
  • func
  • 97.03 %
  • block
  • 99.36 %
  • line
  • 99.55 %
  • branch
  • 91.99 %
  • toggle
  • 91.65 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 53.962us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 16.767us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 14.079us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 4.000s 84.055us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 72.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 606.842us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 14.079us 1 1 100.00
otbn_csr_aliasing 4.000s 72.255us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 104.000s 6918.938us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 37.000s 1135.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 39.000s 141.185us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 42.000s 817.600us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 40.000s 168.500us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 27.000s 270.700us 1 1 100.00
lc_escalation 0 1 0.00
otbn_escalate 6.000s 23.321us 0 1 0.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.795us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 24.070us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 62.871us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 26.725us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 489.457us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 489.457us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 16.767us 1 1 100.00
otbn_csr_rw 3.000s 14.079us 1 1 100.00
otbn_csr_aliasing 4.000s 72.255us 1 1 100.00
otbn_same_csr_outstanding 3.000s 15.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 16.767us 1 1 100.00
otbn_csr_rw 3.000s 14.079us 1 1 100.00
otbn_csr_aliasing 4.000s 72.255us 1 1 100.00
otbn_same_csr_outstanding 3.000s 15.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 67.169us 1 1 100.00
otbn_dmem_err 9.000s 33.019us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 8.000s 86.052us 1 1 100.00
otbn_controller_ispr_rdata_err 6.000s 96.593us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 213.247us 1 1 100.00
otbn_urnd_err 4.000s 27.945us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.887us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 11.000s 49.612us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 52.102us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
otbn_tl_intg_err 11.000s 2285.832us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 4.000s 0.893us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 53.962us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 33.019us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 67.169us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 11.000s 2285.832us 1 1 100.00
sec_cm_controller_fsm_global_esc 0 1 0.00
otbn_escalate 6.000s 23.321us 0 1 0.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 67.169us 1 1 100.00
otbn_dmem_err 9.000s 33.019us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.795us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.887us 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 67.169us 1 1 100.00
otbn_dmem_err 9.000s 33.019us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.795us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.887us 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 0 1 0.00
otbn_escalate 6.000s 23.321us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 67.169us 1 1 100.00
otbn_dmem_err 9.000s 33.019us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 16.795us 1 1 100.00
otbn_illegal_mem_acc 5.000s 10.887us 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 97.128us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 13.567us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 29.000s 202.077us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 29.000s 202.077us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 103.335us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 6.000s 106.123us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 144.575us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 144.575us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 13.877us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 40.000s 168.500us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 16.565us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 16.422us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 1113.697us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 253.000s 2042.761us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 34.011us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_escalate 86454539300558870889581043233725385931194128957096238015033422230211604310110 117
UVM_ERROR @ 23321267 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 23321267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 91300468085048428334503629341153664673149304683042284440418428202223142088922 320
UVM_INFO @ 2042761099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 42013459530815590121056024007323443469845048413318748957070135267948747851294 86
UVM_INFO @ 892705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---