Simulation Results: otp_ctrl

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.79 %
  • code
  • 76.54 %
  • assert
  • 93.99 %
  • func
  • 68.85 %
  • line
  • 88.58 %
  • branch
  • 83.03 %
  • cond
  • 89.85 %
  • toggle
  • 79.21 %
  • FSM
  • 42.01 %
Validation stages
V1
88.89%
V2
85.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.440s 737.131us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.940s 754.048us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.790s 1088.990us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.420s 613.236us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.400s 695.576us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.050s 155.436us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.620s 424.993us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.420s 613.236us 1 1 100.00
otp_ctrl_csr_aliasing 3.050s 155.436us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.170s 62.528us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.130s 125.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.270s 716.510us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.880s 111.807us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 14.750s 2036.195us 0 1 0.00
otp_ctrl_check_fail 3.700s 191.092us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.840s 228.620us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 25.900s 9372.290us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 22.250s 1283.448us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.100s 797.344us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 26.730s 2759.912us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 10.100s 1666.252us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 2.650s 338.327us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 4.400s 4173.449us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.460s 49.262us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.460s 65.903us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.090s 165.891us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.090s 165.891us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.790s 1088.990us 1 1 100.00
otp_ctrl_csr_rw 1.420s 613.236us 1 1 100.00
otp_ctrl_csr_aliasing 3.050s 155.436us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.940s 108.781us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.790s 1088.990us 1 1 100.00
otp_ctrl_csr_rw 1.420s 613.236us 1 1 100.00
otp_ctrl_csr_aliasing 3.050s 155.436us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.940s 108.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
otp_ctrl_tl_intg_err 17.730s 8839.804us 0 1 0.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
otp_ctrl_tl_intg_err 17.730s 8839.804us 0 1 0.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.940s 754.048us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.940s 754.048us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
otp_ctrl_macro_errs 10.100s 1666.252us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
otp_ctrl_macro_errs 10.100s 1666.252us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.470s 176.023us 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.880s 111.807us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 3.700s 191.092us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 25.900s 9372.290us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 25.900s 9372.290us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 25.900s 9372.290us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 25.900s 9372.290us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 25.900s 9372.290us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.940s 754.048us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 25.900s 9372.290us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.940s 754.048us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 126.650s 41871.043us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.840s 228.620us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.940s 754.048us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.940s 754.048us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 10.100s 1666.252us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.720s 6896.722us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.090s 45.935us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 76422532276916112845076227918833606503510850253257641795978004005457608682291 15154
UVM_INFO @ 2036195183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 45391269284099872910697886667735029733201300557688124332607487517171567178895 1578
UVM_INFO @ 4173449378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 19803694565219212626758726137820359861724687441180091274695008674754236885853 10858
UVM_INFO @ 1666252422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 1207399896055850314535875038695218581875900256828075045036939485523178597073 95
UVM_INFO @ 45935274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 66960159959585491037912914128697264371574652718301239992412337752120433496403 92
UVM_INFO @ 424993406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_prim_otp_alert to fire
otp_ctrl_tl_intg_err 51046859675077855518878229670486763104919296894146082045953806868701056315259 250
UVM_INFO @ 8839803522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---