Simulation Results: pattgen

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.92 %
  • code
  • 98.39 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 95.16 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 106.398us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 14.847us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 10.610us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 38.370us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 17.798us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 104.141us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 10.610us 1 1 100.00
pattgen_csr_aliasing 1.000s 17.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 32.000s 1418.299us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 15.000s 6846.750us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 185.430us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 164.000s 23973.098us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 43.230us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 140.979us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 108.607us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 108.607us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 14.847us 1 1 100.00
pattgen_csr_rw 1.000s 10.610us 1 1 100.00
pattgen_csr_aliasing 1.000s 17.798us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 30.150us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 14.847us 1 1 100.00
pattgen_csr_rw 1.000s 10.610us 1 1 100.00
pattgen_csr_aliasing 1.000s 17.798us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 30.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 1.000s 104.985us 1 1 100.00
pattgen_sec_cm 1.000s 264.126us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 104.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 47.000s 6147.268us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 49.298us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 50125442025072617285305024467970292156992759260069480814797272715071477939811 132
UVM_ERROR @ 713170735 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 713170735 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 713272775 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 47945646700656482922909464867880977805880741102289502262716669344600277581366 147
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Name Type Size Value
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exp_item pattgen_item - @10241