Simulation Results: rom_ctrl/32kb

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 97.88 %
  • assert
  • 96.65 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 99.29 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.150s 1014.385us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.930s 176.578us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.260s 409.007us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.350s 165.812us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 200.113us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.040s 210.178us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.260s 409.007us 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 200.113us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.720s 126.785us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.670s 127.397us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.040s 221.576us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.300s 5634.631us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.250s 398.636us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.170s 169.586us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.220s 327.817us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.220s 327.817us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.930s 176.578us 1 1 100.00
rom_ctrl_csr_rw 4.260s 409.007us 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 200.113us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.390s 677.145us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.930s 176.578us 1 1 100.00
rom_ctrl_csr_rw 4.260s 409.007us 1 1 100.00
rom_ctrl_csr_aliasing 3.210s 200.113us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.390s 677.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.520s 1656.588us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 109.430s 976.624us 1 1 100.00
rom_ctrl_tl_intg_err 23.400s 252.444us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 109.430s 976.624us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 109.430s 976.624us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 109.430s 976.624us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 109.430s 976.624us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.150s 1014.385us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.150s 1014.385us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.150s 1014.385us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.400s 252.444us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
rom_ctrl_kmac_err_chk 7.250s 398.636us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.490s 2245.908us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.520s 1656.588us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 109.430s 976.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 166.960s 3708.592us 1 1 100.00