Simulation Results: rom_ctrl/64kb

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.75 %
  • code
  • 99.31 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 97.77 %
  • toggle
  • 99.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.320s 946.633us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.230s 215.073us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.170s 700.143us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.760s 384.209us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.990s 375.235us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.630s 213.589us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.170s 700.143us 1 1 100.00
rom_ctrl_csr_aliasing 5.990s 375.235us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.430s 1115.462us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.180s 1213.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.790s 834.374us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 29.880s 2926.700us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.810s 550.091us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.770s 609.144us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.480s 755.686us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.480s 755.686us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.230s 215.073us 1 1 100.00
rom_ctrl_csr_rw 6.170s 700.143us 1 1 100.00
rom_ctrl_csr_aliasing 5.990s 375.235us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.390s 1032.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.230s 215.073us 1 1 100.00
rom_ctrl_csr_rw 6.170s 700.143us 1 1 100.00
rom_ctrl_csr_aliasing 5.990s 375.235us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.390s 1032.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.920s 2786.641us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 434.400s 577.057us 1 1 100.00
rom_ctrl_tl_intg_err 50.090s 334.267us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 434.400s 577.057us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 434.400s 577.057us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 434.400s 577.057us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 434.400s 577.057us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.320s 946.633us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.320s 946.633us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.320s 946.633us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.090s 334.267us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
rom_ctrl_kmac_err_chk 14.810s 550.091us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 116.960s 28918.864us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.920s 2786.641us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 434.400s 577.057us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 74.880s 5401.830us 1 1 100.00