Simulation Results: rv_timer

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.40 %
  • code
  • 99.84 %
  • assert
  • 96.82 %
  • func
  • 83.53 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.390s 364.780us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.640s 13.905us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 13.056us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.440s 330.750us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.809us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.880s 126.635us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 13.056us 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.780s 111.888us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.950s 797.098us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 164.790s 414308.082us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 164.790s 414308.082us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.600s 32.523us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.520s 13.985us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 167.420us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.310s 130.534us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.310s 130.534us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 13.905us 1 1 100.00
rv_timer_csr_rw 0.550s 13.056us 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.809us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 34.674us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 13.905us 1 1 100.00
rv_timer_csr_rw 0.550s 13.056us 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.809us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 34.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.680s 128.275us 1 1 100.00
rv_timer_tl_intg_err 1.070s 116.585us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.070s 116.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.680s 70.797us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.620s 193.505us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 0.870s 21.633us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 8602395515819289894621182857075753068638208088691558266911280024124484086164 79
UVM_INFO @ 70797093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 14105571577314091589929329614508836515395071411848552048314223179457435858670 75
UVM_INFO @ 111888108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 32246853673481610180888081380007348147637310730409900012912980908056051819819 75
UVM_INFO @ 193505458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
rv_timer_stress_all_with_rand_reset 67690325403937227870176005565960291197135736744201068515596705732866500552212 86
UVM_INFO @ 21632566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---