Simulation Results: spi_device/1r1w

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.31 %
  • code
  • 93.06 %
  • assert
  • 94.64 %
  • func
  • 71.23 %
  • line
  • 99.07 %
  • branch
  • 98.28 %
  • cond
  • 95.06 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 50.460s 15118.708us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.110s 88.336us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.940s 177.418us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.590s 1924.896us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.340s 628.250us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.170s 73.991us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.940s 177.418us 1 1 100.00
spi_device_csr_aliasing 11.340s 628.250us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.730s 11.173us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.900s 45.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.740s 19.763us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.820s 5.773us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.670s 7.118us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.960s 463.359us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.960s 463.359us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.710s 797.777us 1 1 100.00
spi_device_tpm_sts_read 0.830s 37.134us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 6.530s 1617.787us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.900s 13923.700us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.030s 383.579us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.030s 383.579us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.260s 90.500us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.260s 90.500us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.260s 90.500us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.260s 90.500us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.260s 90.500us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 8.490s 2251.434us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 9.940s 1209.612us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 9.940s 1209.612us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 9.940s 1209.612us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.130s 1489.323us 1 1 100.00
spi_device_read_buffer_direct 4.010s 337.936us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 9.940s 1209.612us 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 41.310s 7047.209us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.760s 29.603us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.760s 29.603us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 50.460s 15118.708us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 17.960s 13707.555us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 135.490s 23244.396us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.650s 23.917us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.780s 40.618us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.130s 498.423us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.130s 498.423us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 88.336us 1 1 100.00
spi_device_csr_rw 1.940s 177.418us 1 1 100.00
spi_device_csr_aliasing 11.340s 628.250us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 117.552us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.110s 88.336us 1 1 100.00
spi_device_csr_rw 1.940s 177.418us 1 1 100.00
spi_device_csr_aliasing 11.340s 628.250us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 117.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.320s 110.052us 1 1 100.00
spi_device_tl_intg_err 5.710s 1319.967us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.710s 1319.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 197.170s 48316.800us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 10350139920755818253716857806491369683726529982731215233193665569222473081962 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4522599 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4522599 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[921])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 7654731228175839721631010846236612975930397148754630336483435984113423722596 76
UVM_ERROR @ 4655535 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8d9c28 [100011011001110000101000] vs 0x0 [0])
UVM_ERROR @ 4721535 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcdfff1 [110011011111111111110001] vs 0x0 [0])
UVM_ERROR @ 4745535 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x185d93 [110000101110110010011] vs 0x0 [0])
UVM_ERROR @ 4759535 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa547e7 [101001010100011111100111] vs 0x0 [0])