Simulation Results: spi_device/2p

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.64 %
  • code
  • 94.15 %
  • assert
  • 94.74 %
  • func
  • 77.03 %
  • line
  • 99.10 %
  • branch
  • 98.35 %
  • cond
  • 96.21 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 39.930s 5799.954us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.100s 39.963us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.220s 254.812us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 23.670s 524.517us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.770s 968.595us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.630s 196.348us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.220s 254.812us 1 1 100.00
spi_device_csr_aliasing 15.770s 968.595us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.750s 10.273us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.400s 19.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.680s 44.694us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.970s 18.345us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.860s 21.139us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.410s 621.594us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.410s 621.594us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.140s 10487.873us 1 1 100.00
spi_device_tpm_sts_read 0.860s 21.365us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 30.630s 7340.070us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 9.590s 16395.726us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.960s 104.461us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.960s 104.461us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 16.190s 10858.188us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 16.190s 10858.188us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 16.190s 10858.188us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 16.190s 10858.188us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 16.190s 10858.188us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.050s 1828.106us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.080s 1476.832us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.080s 1476.832us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.080s 1476.832us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.140s 1854.089us 1 1 100.00
spi_device_read_buffer_direct 4.740s 3374.987us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.080s 1476.832us 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.830s 31.987us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.200s 53.404us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.200s 53.404us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 39.930s 5799.954us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 146.360s 23303.481us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 276.190s 83348.925us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.810s 14.878us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.800s 24.658us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.780s 32.172us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.780s 32.172us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.100s 39.963us 1 1 100.00
spi_device_csr_rw 2.220s 254.812us 1 1 100.00
spi_device_csr_aliasing 15.770s 968.595us 1 1 100.00
spi_device_same_csr_outstanding 1.970s 226.133us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.100s 39.963us 1 1 100.00
spi_device_csr_rw 2.220s 254.812us 1 1 100.00
spi_device_csr_aliasing 15.770s 968.595us 1 1 100.00
spi_device_same_csr_outstanding 1.970s 226.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.930s 359.623us 1 1 100.00
spi_device_tl_intg_err 4.990s 432.388us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 4.990s 432.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 228.570s 795278.914us 1 1 100.00