Simulation Results: sram_ctrl/main

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 94.43 %
  • assert
  • 96.33 %
  • func
  • 97.03 %
  • line
  • 98.91 %
  • branch
  • 97.90 %
  • cond
  • 94.94 %
  • toggle
  • 89.90 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.310s 785.525us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.020s 27.871us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.990s 12.655us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.230s 168.489us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 58.285us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.250s 1384.366us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.990s 12.655us 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 58.285us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 250.670s 35935.795us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 108.180s 12869.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 41.740s 7664.612us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 285.580s 19352.100us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 404.530s 8209.932us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 56.370s 19737.614us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 57.560s 130227.948us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 30.650s 12514.162us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.820s 2761.078us 1 1 100.00
sram_ctrl_partial_access_b2b 160.420s 16640.731us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.590s 1362.745us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.550s 790.098us 1 1 100.00
sram_ctrl_throughput_w_readback 4.470s 1371.197us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 9.900s 1389.864us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.160s 693.705us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2446.130s 54280.258us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.970s 35.295us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.270s 222.132us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.270s 222.132us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.020s 27.871us 1 1 100.00
sram_ctrl_csr_rw 0.990s 12.655us 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 58.285us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 63.924us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.020s 27.871us 1 1 100.00
sram_ctrl_csr_rw 0.990s 12.655us 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 58.285us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.740s 63.924us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.160s 7573.780us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.100s 248.861us 1 1 100.00
sram_ctrl_tl_intg_err 2.730s 691.100us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.100s 248.861us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.730s 691.100us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.900s 1389.864us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.900s 1389.864us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.990s 12.655us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 30.650s 12514.162us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.650s 12514.162us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 30.650s 12514.162us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 57.560s 130227.948us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.630s 2911.807us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.160s 7573.780us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.460s 706.818us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.310s 785.525us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.310s 785.525us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 30.650s 12514.162us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.100s 248.861us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 57.560s 130227.948us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.100s 248.861us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.100s 248.861us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.310s 785.525us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.100s 248.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 18.180s 895.581us 1 1 100.00