Simulation Results: sram_ctrl/ret

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.81 %
  • code
  • 94.15 %
  • assert
  • 96.43 %
  • func
  • 96.85 %
  • line
  • 98.78 %
  • branch
  • 97.39 %
  • cond
  • 94.25 %
  • toggle
  • 89.85 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.090s 188.670us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.750s 30.079us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.670s 39.744us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.200s 180.898us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 31.461us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.120s 49.080us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.670s 39.744us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 31.461us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.720s 694.776us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.700s 99.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.010s 3111.426us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 248.950s 3514.645us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 33.940s 3203.055us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 2.350s 71.866us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.850s 2589.892us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.430s 670.373us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.170s 52.093us 1 1 100.00
sram_ctrl_partial_access_b2b 151.750s 33019.810us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.170s 125.273us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.140s 83.128us 1 1 100.00
sram_ctrl_throughput_w_readback 1.190s 72.194us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 1.840s 88.883us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.920s 32.477us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 25.010s 7403.120us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.730s 29.164us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.450s 127.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.450s 127.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.750s 30.079us 1 1 100.00
sram_ctrl_csr_rw 0.670s 39.744us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 31.461us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.850s 103.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.750s 30.079us 1 1 100.00
sram_ctrl_csr_rw 0.670s 39.744us 1 1 100.00
sram_ctrl_csr_aliasing 0.890s 31.461us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.850s 103.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.530s 232.104us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.310s 386.357us 1 1 100.00
sram_ctrl_tl_intg_err 1.850s 274.213us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.310s 386.357us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.850s 274.213us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 1.840s 88.883us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 1.840s 88.883us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.670s 39.744us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.430s 670.373us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.430s 670.373us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.430s 670.373us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.850s 2589.892us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.110s 153.954us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.530s 232.104us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 0.940s 97.391us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.090s 188.670us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.090s 188.670us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.430s 670.373us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.310s 386.357us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.850s 2589.892us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.310s 386.357us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.310s 386.357us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.090s 188.670us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.310s 386.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 40.960s 2081.352us 1 1 100.00