Simulation Results: sysrst_ctrl

 
14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.16 %
  • code
  • 93.64 %
  • assert
  • 95.31 %
  • func
  • 60.53 %
  • line
  • 97.75 %
  • branch
  • 97.78 %
  • cond
  • 95.10 %
  • toggle
  • 100.00 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.290s 2115.507us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.580s 2472.022us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 5.510s 2387.295us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.520s 2343.413us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.470s 6062.004us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.350s 2052.201us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 18.750s 39085.786us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.960s 2537.351us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 5.150s 2048.355us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.350s 2052.201us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.960s 2537.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 155.340s 73782.830us 1 1 100.00
combo_detect_with_pre_cond 0 1 0.00
sysrst_ctrl_combo_detect_with_pre_cond 30.340s 15137.217us 0 1 0.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.470s 3356.139us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 7.190s 3688.558us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.170s 2517.645us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.920s 2063.749us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.260s 3411.142us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.040s 2679.949us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.060s 5494.047us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 21.100s 42990.423us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 5.540s 10280.736us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.380s 2013.410us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.080s 2025.200us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.170s 2037.187us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.170s 2037.187us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.470s 6062.004us 1 1 100.00
sysrst_ctrl_csr_rw 4.350s 2052.201us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.960s 2537.351us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.500s 9653.428us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.470s 6062.004us 1 1 100.00
sysrst_ctrl_csr_rw 4.350s 2052.201us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.960s 2537.351us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 19.500s 9653.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 19.970s 42131.472us 1 1 100.00
sysrst_ctrl_tl_intg_err 11.320s 22316.999us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 11.320s 22316.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 12.270s 5779.659us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])
sysrst_ctrl_combo_detect_with_pre_cond 14386411237718255368824534611437152528825878963466508520925370061826325934848 671
UVM_INFO @ 14922190869 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 14942190869 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_ERROR @ 15137217307 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 2 [0x2])
UVM_INFO @ 15137217307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]