Simulation Results

Simulation Results: uart

14/04/2026 16:33:31 DVSim: v1.30.1 sha: 7caff13 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.46 %

code
95.76 %

assert
97.12 %

func
51.50 %

line
99.17 %

branch
97.44 %

cond
94.87 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	1.900s	670.641us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.840s	33.479us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.770s	15.330us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.760s	667.303us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.730s	15.773us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.800s	30.096us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.770s	15.330us	1	1	100.00
	uart_csr_aliasing	0.730s	15.773us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	13.680s	41452.711us	1	1	100.00
parity				2	2	100.00
	uart_smoke	1.900s	670.641us	1	1	100.00
	uart_tx_rx	13.680s	41452.711us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	23.190s	72534.467us	1	1	100.00
	uart_rx_parity_err	17.230s	29255.102us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	13.680s	41452.711us	1	1	100.00
	uart_intr	23.190s	72534.467us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	24.270s	66826.810us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	38.000s	131680.239us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	29.740s	97818.482us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	23.190s	72534.467us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	23.190s	72534.467us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	23.190s	72534.467us	1	1	100.00
perf				1	1	100.00
	uart_perf	105.720s	5207.229us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	6.260s	7289.831us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	6.260s	7289.831us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	2.300s	3215.165us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	2.770s	5586.250us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	2.630s	1241.629us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	35.420s	5710.524us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	395.750s	119585.462us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	39.330s	196611.225us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.640s	12.160us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.690s	103.851us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	0.930s	221.433us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	0.930s	221.433us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.840s	33.479us	1	1	100.00
	uart_csr_rw	0.770s	15.330us	1	1	100.00
	uart_csr_aliasing	0.730s	15.773us	1	1	100.00
	uart_same_csr_outstanding	0.940s	24.069us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.840s	33.479us	1	1	100.00
	uart_csr_rw	0.770s	15.330us	1	1	100.00
	uart_csr_aliasing	0.730s	15.773us	1	1	100.00
	uart_same_csr_outstanding	0.940s	24.069us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	0.760s	151.261us	1	1	100.00
	uart_tl_intg_err	0.990s	621.661us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	0.990s	621.661us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	38.670s	28506.237us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:
	uart_noise_filter	96506847850691956917949462913998484039641659558129960497180325855135888518576	74	UVM_ERROR @ 1179604540 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 1179844540 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 1179884540 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 1180084540 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *
	uart_stress_all_with_rand_reset	37045101155868730328487037042936948464461521383997207085780025572274985307081	100	UVM_ERROR @ 6255924019 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 6367111519 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/356 UVM_INFO @ 6798611519 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/356 UVM_INFO @ 6949986519 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/356