Simulation Results: adc_ctrl

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.61 %
  • code
  • 97.47 %
  • assert
  • 95.95 %
  • func
  • 18.41 %
  • line
  • 99.02 %
  • branch
  • 97.71 %
  • cond
  • 93.34 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.180s 5844.442us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.340s 1339.952us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.680s 553.129us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 20.810s 25793.541us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.560s 779.778us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.020s 407.118us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.680s 553.129us 1 1 100.00
adc_ctrl_csr_aliasing 1.560s 779.778us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 33.630s 18487.638us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 8.010s 17117.062us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 19.460s 34663.848us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 29.480s 17425.374us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 24.710s 26425.353us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 9.140s 22891.643us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 34.620s 72300.192us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 5.670s 19550.813us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 9.990s 5168.070us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 43.110s 27083.828us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 231.900s 141876.806us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 96.990s 87513.088us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.960s 317.837us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.270s 520.066us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.640s 704.461us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.640s 704.461us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.340s 1339.952us 1 1 100.00
adc_ctrl_csr_rw 1.680s 553.129us 1 1 100.00
adc_ctrl_csr_aliasing 1.560s 779.778us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.940s 2862.408us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.340s 1339.952us 1 1 100.00
adc_ctrl_csr_rw 1.680s 553.129us 1 1 100.00
adc_ctrl_csr_aliasing 1.560s 779.778us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.940s 2862.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.970s 7893.804us 1 1 100.00
adc_ctrl_tl_intg_err 2.440s 5559.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.440s 5559.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 136.020s 465911.487us 1 1 100.00