Simulation Results: aes/masked

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.53 %
  • code
  • 95.25 %
  • assert
  • 98.29 %
  • func
  • 66.06 %
  • block
  • 95.91 %
  • line
  • 97.66 %
  • branch
  • 89.80 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 67.042us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 64.718us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 55.973us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 87.399us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1205.797us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 151.058us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 85.591us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 87.399us 1 1 100.00
aes_csr_aliasing 2.000s 151.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 64.718us 1 1 100.00
aes_config_error 3.000s 126.440us 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 64.718us 1 1 100.00
aes_config_error 3.000s 126.440us 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 258.288us 1 1 100.00
aes_b2b 21.000s 506.041us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 64.718us 1 1 100.00
aes_config_error 3.000s 126.440us 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
aes_alert_reset 4.000s 122.894us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 128.315us 1 1 100.00
aes_config_error 3.000s 126.440us 1 1 100.00
aes_alert_reset 4.000s 122.894us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 61.965us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 404.046us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 3644.879us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 122.894us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 258.288us 1 1 100.00
aes_sideload 21.000s 1550.885us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 6.000s 309.294us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 29.000s 4196.090us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 80.446us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 66.076us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 226.622us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 226.622us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.973us 1 1 100.00
aes_csr_rw 2.000s 87.399us 1 1 100.00
aes_csr_aliasing 2.000s 151.058us 1 1 100.00
aes_same_csr_outstanding 2.000s 214.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.973us 1 1 100.00
aes_csr_rw 2.000s 87.399us 1 1 100.00
aes_csr_aliasing 2.000s 151.058us 1 1 100.00
aes_same_csr_outstanding 2.000s 214.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 63.612us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 275.202us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 275.202us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 275.202us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 275.202us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 1384.239us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1888.124us 1 1 100.00
aes_tl_intg_err 2.000s 712.781us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 712.781us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 122.894us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 275.202us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 275.202us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 64.718us 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
aes_alert_reset 4.000s 122.894us 1 1 100.00
aes_core_fi 3.000s 197.599us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 80.446us 1 1 100.00
aes_config_error 3.000s 126.440us 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
aes_core_fi 3.000s 197.599us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 275.202us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 52.574us 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 258.288us 1 1 100.00
aes_sideload 21.000s 1550.885us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 52.574us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 52.574us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 52.574us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 52.574us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 52.574us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 258.288us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 210.137us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
aes_ctr_fi 3.000s 268.036us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 210.137us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 210.137us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_ctr_fi 3.000s 268.036us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 210.137us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
aes_ctr_fi 3.000s 268.036us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 122.894us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
aes_ctr_fi 3.000s 268.036us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
aes_ctr_fi 3.000s 268.036us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_ctr_fi 3.000s 268.036us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_ghash_fi 2.000s 54.027us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 210.137us 1 1 100.00
aes_control_fi 3.000s 55.011us 1 1 100.00
aes_cipher_fi 3.000s 52.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 34.805us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 3392886407871382489205733449628157107003824164347772584976351137755492737293 142
UVM_INFO @ 34804897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---