Simulation Results: aes/unmasked

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.12 %
  • code
  • 92.03 %
  • assert
  • 97.75 %
  • func
  • 65.59 %
  • block
  • 92.47 %
  • line
  • 94.21 %
  • branch
  • 86.55 %
  • toggle
  • 97.99 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 62.778us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 121.737us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 61.592us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.789us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 989.509us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 148.083us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 262.857us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.789us 1 1 100.00
aes_csr_aliasing 2.000s 148.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 121.737us 1 1 100.00
aes_config_error 2.000s 110.829us 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 121.737us 1 1 100.00
aes_config_error 2.000s 110.829us 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 185.950us 1 1 100.00
aes_b2b 6.000s 216.051us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 121.737us 1 1 100.00
aes_config_error 2.000s 110.829us 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
aes_alert_reset 2.000s 108.462us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 77.592us 1 1 100.00
aes_config_error 2.000s 110.829us 1 1 100.00
aes_alert_reset 2.000s 108.462us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 148.505us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 115.115us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 183.596us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 108.462us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 185.950us 1 1 100.00
aes_sideload 2.000s 104.935us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 78.071us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 11.000s 198.822us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 92.127us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.388us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 120.739us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 120.739us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.592us 1 1 100.00
aes_csr_rw 2.000s 77.789us 1 1 100.00
aes_csr_aliasing 2.000s 148.083us 1 1 100.00
aes_same_csr_outstanding 2.000s 109.673us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.592us 1 1 100.00
aes_csr_rw 2.000s 77.789us 1 1 100.00
aes_csr_aliasing 2.000s 148.083us 1 1 100.00
aes_same_csr_outstanding 2.000s 109.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 96.091us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 86.255us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 86.255us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 86.255us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 86.255us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 131.022us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1542.247us 1 1 100.00
aes_tl_intg_err 3.000s 600.705us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 600.705us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 108.462us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.255us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.255us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 121.737us 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
aes_alert_reset 2.000s 108.462us 1 1 100.00
aes_core_fi 2.000s 91.227us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 92.127us 1 1 100.00
aes_config_error 2.000s 110.829us 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
aes_core_fi 2.000s 91.227us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 86.255us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 72.836us 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 185.950us 1 1 100.00
aes_sideload 2.000s 104.935us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.836us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 72.836us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 72.836us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 72.836us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 72.836us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 185.950us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 663.557us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
aes_ctr_fi 2.000s 67.699us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 663.557us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 663.557us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_ctr_fi 2.000s 67.699us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 663.557us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
aes_ctr_fi 2.000s 67.699us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 108.462us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
aes_ctr_fi 2.000s 67.699us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
aes_ctr_fi 2.000s 67.699us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_ctr_fi 2.000s 67.699us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_ghash_fi 2.000s 71.044us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 663.557us 1 1 100.00
aes_control_fi 1.000s 66.771us 1 1 100.00
aes_cipher_fi 2.000s 61.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 11.000s 216.813us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS)
aes_stress_all_with_rand_reset 101164746444597924766115426664079639731888700918245436613965947121376017846842 465
UVM_ERROR @ 216813394 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 216813394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---