Simulation Results: alert_handler

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.05 %
  • code
  • 90.46 %
  • assert
  • 97.77 %
  • func
  • 78.93 %
  • line
  • 99.61 %
  • branch
  • 98.22 %
  • cond
  • 90.60 %
  • toggle
  • 92.91 %
  • FSM
  • 70.97 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 10.110s 615.490us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.140s 526.062us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 6.140s 96.754us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 71.880s 847.925us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 138.450s 3494.754us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.770s 105.806us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 6.140s 96.754us 1 1 100.00
alert_handler_csr_aliasing 138.450s 3494.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 100.290s 4141.162us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 35.890s 14190.196us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1486.990s 38487.787us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 14.010s 366.576us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 10.110s 615.490us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 11.820s 293.681us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 29.620s 3539.858us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 55.320s 9388.338us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1040.170s 111477.975us 1 1 100.00
alert_handler_lpg_stub_clk 441.090s 35027.325us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1297.490s 123171.443us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 6.640s 392.429us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.650s 21.585us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.010s 34.068us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.090s 76.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.090s 76.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.140s 526.062us 1 1 100.00
alert_handler_csr_rw 6.140s 96.754us 1 1 100.00
alert_handler_csr_aliasing 138.450s 3494.754us 1 1 100.00
alert_handler_same_csr_outstanding 12.550s 366.891us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.140s 526.062us 1 1 100.00
alert_handler_csr_rw 6.140s 96.754us 1 1 100.00
alert_handler_csr_aliasing 138.450s 3494.754us 1 1 100.00
alert_handler_same_csr_outstanding 12.550s 366.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 70.860s 3435.744us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 70.860s 3435.744us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 70.860s 3435.744us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 70.860s 3435.744us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 820.690s 17131.342us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
alert_handler_tl_intg_err 16.940s 698.492us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 16.940s 698.492us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 70.860s 3435.744us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 10.110s 615.490us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 10.110s 615.490us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 10.110s 615.490us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 10.110s 615.490us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 14.010s 366.576us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1040.170s 111477.975us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 14.010s 366.576us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1486.990s 38487.787us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1486.990s 38487.787us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.960s 590.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 40.510s 1073.123us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 110530049195930591409998042783889382268395020435287761369825459472556284243105 93
UVM_INFO @ 9388338447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 44107174052093958862808012703866193632820216057665184339083701653131204795845 94
UVM_INFO @ 1073122868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---