Simulation Results

Simulation Results: chip

15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
76.03 %

code
85.24 %

assert
97.50 %

func
45.35 %

line
94.38 %

branch
93.55 %

cond
89.81 %

toggle
91.32 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		79.14%
V2S		50.00%
V3		65.38%
unmapped		80.00%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	143.060s	2614.509us	1	1	100.00
	chip_sw_example_rom	73.540s	2442.916us	1	1	100.00
	chip_sw_example_manufacturer	207.210s	3475.186us	1	1	100.00
	chip_sw_example_concurrency	123.140s	3138.187us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	306.660s	8317.372us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	391.150s	5319.837us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	197.980s	3615.059us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4865.380s	38211.538us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	353.030s	6217.182us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4865.380s	38211.538us	1	1	100.00
	chip_csr_rw	391.150s	5319.837us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	5.940s	171.527us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	258.250s	4274.412us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	258.250s	4274.412us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	258.250s	4274.412us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	393.370s	4876.234us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	393.370s	4876.234us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	375.270s	4345.767us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	369.030s	4609.878us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	380.360s	4729.928us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1024.450s	8669.909us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1012.160s	8119.114us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	610.910s	9486.509us	1	1	100.00

220/278 passed

79.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	191.200s	4473.310us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	191.200s	4473.310us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	174.710s	3170.563us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	151.940s	3294.702us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	152.610s	3290.033us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	100.770s	2543.111us	1	1	100.00
	chip_tap_straps_testunlock0	241.950s	4807.892us	1	1	100.00
	chip_tap_straps_rma	318.910s	5666.015us	1	1	100.00
	chip_tap_straps_prod	77.950s	2781.158us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	142.690s	3096.068us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	869.740s	9286.094us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	409.540s	6000.505us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	409.540s	6000.505us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	590.030s	7443.991us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1907.810s	16100.426us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	372.230s	4328.152us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	603.200s	6385.014us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3585.120s	18942.526us	1	1	100.00
	chip_sw_aes_enc_jitter_en	222.350s	3203.581us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	624.380s	7698.257us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	130.790s	2512.388us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1467.620s	11394.657us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	212.370s	3305.220us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	348.150s	4604.258us	1	1	100.00
	chip_sw_clkmgr_jitter	183.200s	3574.526us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	205.800s	3493.133us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	406.560s	6013.038us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	248.750s	4991.520us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	173.400s	2469.721us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	248.750s	4991.520us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	118.850s	2715.048us	1	1	100.00
	chip_sw_aes_smoketest	195.150s	3405.592us	1	1	100.00
	chip_sw_aon_timer_smoketest	203.900s	3365.710us	1	1	100.00
	chip_sw_clkmgr_smoketest	170.460s	2423.888us	1	1	100.00
	chip_sw_csrng_smoketest	169.360s	3000.052us	1	1	100.00
	chip_sw_entropy_src_smoketest	928.340s	7456.201us	1	1	100.00
	chip_sw_gpio_smoketest	190.810s	2979.205us	1	1	100.00
	chip_sw_hmac_smoketest	227.890s	3566.324us	1	1	100.00
	chip_sw_kmac_smoketest	208.790s	3440.665us	1	1	100.00
	chip_sw_otbn_smoketest	788.380s	6796.986us	1	1	100.00
	chip_sw_pwrmgr_smoketest	281.110s	6315.638us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	282.790s	6772.801us	1	1	100.00
	chip_sw_rv_plic_smoketest	134.240s	3103.912us	1	1	100.00
	chip_sw_rv_timer_smoketest	128.810s	3051.295us	1	1	100.00
	chip_sw_rstmgr_smoketest	130.980s	2909.114us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	191.970s	2646.449us	1	1	100.00
	chip_sw_uart_smoketest	153.800s	2921.664us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	108.890s	2923.499us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	343.310s	4720.624us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7894.820s	63162.077us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3184.880s	18010.902us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	40.970s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	221.080s	2792.023us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	173.730s	2715.580us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7381.380s	56203.664us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7456.420s	57248.955us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	146.540s	3257.559us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	146.540s	3257.559us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4865.380s	38211.538us	1	1	100.00
	chip_same_csr_outstanding	2476.900s	29435.913us	1	1	100.00
	chip_csr_hw_reset	306.660s	8317.372us	1	1	100.00
	chip_csr_rw	391.150s	5319.837us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4865.380s	38211.538us	1	1	100.00
	chip_same_csr_outstanding	2476.900s	29435.913us	1	1	100.00
	chip_csr_hw_reset	306.660s	8317.372us	1	1	100.00
	chip_csr_rw	391.150s	5319.837us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	37.850s	1733.246us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	6.690s	46.582us	1	1	100.00
	xbar_smoke_large_delays	47.450s	7497.994us	1	1	100.00
	xbar_smoke_slow_rsp	26.920s	2654.899us	1	1	100.00
	xbar_random_zero_delays	19.810s	282.181us	1	1	100.00
	xbar_random_large_delays	167.480s	28925.485us	1	1	100.00
	xbar_random_slow_rsp	28.780s	2927.369us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	40.960s	1310.592us	1	1	100.00
	xbar_error_and_unmapped_addr	17.540s	680.029us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	24.870s	461.582us	1	1	100.00
	xbar_error_and_unmapped_addr	17.540s	680.029us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	7.900s	103.540us	1	1	100.00
	xbar_access_same_device_slow_rsp	371.590s	42788.039us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	23.450s	451.854us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	26.390s	395.463us	1	1	100.00
	xbar_stress_all_with_error	137.480s	6036.774us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	157.170s	2218.724us	1	1	100.00
	xbar_stress_all_with_reset_error	420.280s	14202.304us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3184.880s	18010.902us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2619.570s	31151.659us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3008.510s	15845.227us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	52.812s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	15.891s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	8.354s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16.446s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	7.886s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	53.491s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	60.356s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	37.629s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	112.323s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	9.903s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	210.522s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	102.797s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	90.528s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	155.956s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	83.356s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.080s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	21.460s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	16.490s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.450s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	16.730s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	20.640s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.740s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.570s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.190s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.960s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.350s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.750s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.670s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.750s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.050s	10.400us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	205.568s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	104.326s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	135.235s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	19.658s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	79.485s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	5698.710s	28572.155us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3086.690s	17074.560us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5870.030s	29430.210us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3156.250s	16183.496us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2820.780s	34591.428us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2820.780s	34591.428us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	159.820s	2896.870us	1	1	100.00
	chip_sw_aes_enc_jitter_en	222.350s	3203.581us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	186.550s	3007.641us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	200.970s	2830.268us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1656.480s	12987.580us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	182.620s	3312.952us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	406.580s	4900.508us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	432.890s	5645.429us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	521.040s	5573.192us	1	1	100.00
	chip_plic_all_irqs_10	338.870s	3961.525us	1	1	100.00
	chip_plic_all_irqs_20	377.830s	4378.946us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	206.480s	3359.610us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	894.620s	10542.675us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	261.910s	5223.307us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	171.210s	3382.366us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	0.000s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	815.860s	6761.053us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1100.230s	8729.107us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	753.150s	8336.254us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9119.580s	256353.157us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	289.630s	4088.829us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	281.110s	6315.638us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	289.630s	4088.829us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	501.180s	8316.832us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	501.180s	8316.832us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	261.890s	7006.298us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	370.990s	5835.817us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	581.860s	6819.697us	1	1	100.00
	chip_sw_aes_idle	200.970s	2830.268us	1	1	100.00
	chip_sw_hmac_enc_idle	178.510s	3339.595us	1	1	100.00
	chip_sw_kmac_idle	176.300s	2993.920us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	326.250s	5127.579us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	346.430s	4698.276us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	306.360s	4641.988us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	352.670s	4721.133us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	663.160s	9158.243us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	423.880s	4421.090us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	354.100s	4760.718us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	341.440s	3732.244us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	343.460s	4525.860us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	378.550s	4102.959us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	379.990s	4927.687us	1	1	100.00
	chip_sw_ast_clk_outputs	590.030s	7443.991us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	362.240s	5868.553us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	341.440s	3732.244us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	343.460s	4525.860us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	372.230s	4328.152us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	603.200s	6385.014us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3585.120s	18942.526us	1	1	100.00
	chip_sw_aes_enc_jitter_en	222.350s	3203.581us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	624.380s	7698.257us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	130.790s	2512.388us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1467.620s	11394.657us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	212.370s	3305.220us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	348.150s	4604.258us	1	1	100.00
	chip_sw_clkmgr_jitter	183.200s	3574.526us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	148.370s	3551.670us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	409.850s	5197.959us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	640.910s	6977.283us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3790.230s	24610.517us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	171.870s	3543.564us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	151.530s	3467.721us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	724.320s	7914.315us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	192.540s	3947.759us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	352.180s	6421.952us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1113.570s	23180.238us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	1692.260s	14054.657us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	590.030s	7443.991us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	385.870s	4419.839us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	265.670s	3846.041us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	432.890s	5645.429us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	815.860s	6761.053us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1132.770s	7989.971us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	123.800s	3529.011us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	564.410s	6896.208us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	174.570s	2987.053us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2535.400s	15671.141us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	177.390s	3079.210us	1	1	100.00
	chip_sw_edn_entropy_reqs	617.570s	6740.312us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	177.390s	3079.210us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1132.770s	7989.971us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	137.380s	2471.143us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	937.230s	15731.042us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	538.170s	5733.518us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	603.200s	6385.014us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	342.480s	3999.298us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	372.230s	4328.152us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3427.830s	43502.677us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	937.230s	15731.042us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	188.280s	3449.224us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	824.970s	6715.861us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	167.760s	2918.033us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3427.830s	43502.677us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	167.760s	2918.033us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	167.760s	2918.033us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	167.760s	2918.033us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	167.760s	2918.033us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	432.890s	5645.429us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	263.110s	9101.529us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	565.530s	5015.253us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	432.880s	4621.447us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	432.880s	4621.447us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	167.370s	3401.990us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	130.790s	2512.388us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	178.510s	3339.595us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1668.230s	11124.329us	1	1	100.00
chip_sw_hmac_multistream_mode				1	1	100.00
	chip_sw_hmac_multistream	666.550s	5983.550us	1	1	100.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	383.330s	5037.007us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	342.080s	4575.041us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	327.360s	4541.426us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	281.990s	4015.966us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	824.970s	6715.861us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1467.620s	11394.657us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1409.040s	11464.676us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1656.480s	12987.580us	1	1	100.00
chip_sw_keymgr_sideload_otbn				1	1	100.00
	chip_sw_keymgr_sideload_otbn	2245.000s	12862.099us	1	1	100.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	154.900s	2831.872us	1	1	100.00
	chip_sw_kmac_mode_kmac	185.060s	2952.605us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	212.370s	3305.220us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	824.970s	6715.861us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	188.120s	2794.987us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1376.620s	10351.046us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	176.300s	2993.920us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	406.580s	4900.508us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	100.770s	2543.111us	1	1	100.00
	chip_tap_straps_rma	318.910s	5666.015us	1	1	100.00
	chip_tap_straps_prod	77.950s	2781.158us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	133.030s	3378.903us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1102.270s	9467.026us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	167.760s	2918.033us	0	1	0.00
	chip_sw_flash_rma_unlocked	3427.830s	43502.677us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	213.080s	2973.903us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	531.180s	7576.079us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	641.650s	8269.641us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	499.500s	6584.609us	0	1	0.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
	chip_sw_keymgr_key_derivation	824.970s	6715.861us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	393.610s	9180.193us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	636.120s	9555.261us	1	1	100.00
	chip_prim_tl_access	263.110s	9101.529us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	362.240s	5868.553us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	423.880s	4421.090us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	354.100s	4760.718us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	341.440s	3732.244us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	343.460s	4525.860us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	378.550s	4102.959us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	379.990s	4927.687us	1	1	100.00
	chip_tap_straps_dev	100.770s	2543.111us	1	1	100.00
	chip_tap_straps_rma	318.910s	5666.015us	1	1	100.00
	chip_tap_straps_prod	77.950s	2781.158us	1	1	100.00
	chip_rv_dm_lc_disabled	48.120s	2080.840us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	188.330s	3424.247us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	78.280s	3575.697us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	98.510s	3437.043us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	79.690s	3664.548us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1476.310s	25849.298us	1	1	100.00
	chip_rv_dm_lc_disabled	48.120s	2080.840us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	689.400s	10012.583us	0	1	0.00
	chip_sw_lc_walkthrough_prod	603.080s	9557.566us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	694.060s	9808.569us	1	1	100.00
	chip_sw_lc_walkthrough_rma	388.600s	6491.498us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1476.310s	25849.298us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	60.640s	2720.395us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	60.940s	2351.135us	1	1	100.00
	rom_volatile_raw_unlock	141.986s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3432.770s	16796.183us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3585.120s	18942.526us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	581.860s	6819.697us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	581.860s	6819.697us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	581.860s	6819.697us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	274.510s	3666.166us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	937.230s	15731.042us	1	1	100.00
	chip_sw_otbn_mem_scramble	274.510s	3666.166us	1	1	100.00
	chip_sw_keymgr_key_derivation	824.970s	6715.861us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	362.570s	5839.585us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	187.530s	3216.363us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	937.230s	15731.042us	1	1	100.00
	chip_sw_otbn_mem_scramble	274.510s	3666.166us	1	1	100.00
	chip_sw_keymgr_key_derivation	824.970s	6715.861us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	362.570s	5839.585us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	187.530s	3216.363us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	440.330s	6680.348us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	133.030s	3378.903us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	213.080s	2973.903us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	531.180s	7576.079us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	641.650s	8269.641us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	499.500s	6584.609us	0	1	0.00
	chip_sw_lc_ctrl_transition	415.540s	7352.163us	1	1	100.00
	chip_prim_tl_access	263.110s	9101.529us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	263.110s	9101.529us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	942.010s	7783.370us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	243.840s	7214.717us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	690.800s	22161.109us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	227.100s	7419.981us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	348.320s	7318.975us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	438.260s	6225.763us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1084.400s	24025.987us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	441.400s	9864.665us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	501.180s	8316.832us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	870.750s	10430.990us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	386.000s	5663.267us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	243.840s	7214.717us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	246.100s	4934.699us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	2400.450s	33647.281us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	256.400s	7006.261us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	260.150s	5385.050us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1727.630s	22491.459us	1	1	100.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	581.320s	7437.123us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	860.940s	11097.571us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1450.720s	22914.452us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	186.170s	3315.680us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	432.890s	5645.429us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	393.610s	9180.193us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	393.610s	9180.193us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				4	4	100.00
	chip_sw_pwrmgr_all_reset_reqs	860.940s	11097.571us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1727.630s	22491.459us	1	1	100.00
	chip_sw_pwrmgr_wdog_reset	386.000s	5663.267us	1	1	100.00
	chip_sw_pwrmgr_smoketest	281.110s	6315.638us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	225.690s	5029.434us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	299.990s	4953.745us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	349.750s	4803.385us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	894.620s	10542.675us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	142.160s	2991.691us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	432.890s	5645.429us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1100.230s	8729.107us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	421.240s	4657.246us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	460.860s	4325.225us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	159.990s	3072.741us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	187.530s	3216.363us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	299.990s	4953.745us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	299.990s	4953.745us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	618.980s	10749.666us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	938.980s	13566.008us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	225.690s	5029.434us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	185.410s	3578.118us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	250.100s	6598.250us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	318.910s	5666.015us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	48.120s	2080.840us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	521.040s	5573.192us	1	1	100.00
	chip_plic_all_irqs_10	338.870s	3961.525us	1	1	100.00
	chip_plic_all_irqs_20	377.830s	4378.946us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	171.110s	2899.813us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	151.810s	2945.848us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3184.880s	18010.902us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	407.900s	5907.849us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	249.630s	3955.356us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	174.750s	3310.619us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	159.900s	3023.817us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	362.570s	5839.585us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	348.150s	4604.258us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	449.010s	9379.208us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	361.880s	7987.804us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	636.120s	9555.261us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	432.890s	5645.429us	1	1	100.00
	chip_sw_data_integrity_escalation	409.540s	6000.505us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	581.320s	7437.123us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1184.160s	25599.719us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	175.230s	3500.593us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	242.980s	3829.599us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	346.660s	4898.140us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1184.160s	25599.719us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1184.160s	25599.719us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2394.150s	20633.428us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2394.150s	20633.428us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	337.760s	6467.303us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2820.780s	34591.428us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	169.090s	3011.580us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	145.840s	2814.949us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	329.850s	4000.202us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	293.910s	3703.109us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	990.330s	8659.732us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5213.760s	32076.585us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1779.730s	12303.113us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	151.280s	3044.260us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	194.550s	2995.576us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	89.500s	2573.900us	0	1	0.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9709.990s	71216.976us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1068.710s	6523.306us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	165.130s	2980.121us	0	1	0.00
	rom_e2e_jtag_debug_dev	539.330s	14191.126us	0	1	0.00
	rom_e2e_jtag_debug_rma	444.420s	6670.324us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	75.970s	2467.171us	0	1	0.00
	rom_e2e_jtag_inject_dev	64.990s	2818.553us	0	1	0.00
	rom_e2e_jtag_inject_rma	67.000s	2168.659us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	133.424s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	217.030s	3220.316us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	349.880s	3405.402us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	506.130s	4402.628us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	911.570s	7260.564us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	210.650s	2261.031us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	549.500s	5539.676us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	114.290s	2659.807us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	191.060s	3454.560us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	222.440s	5462.199us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	297.120s	4341.329us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	860.940s	11097.571us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	165.130s	2980.121us	0	1	0.00
	rom_e2e_jtag_debug_dev	539.330s	14191.126us	0	1	0.00
	rom_e2e_jtag_debug_rma	444.420s	6670.324us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	305.150s	4857.693us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	432.890s	5645.429us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5778.470s	38853.464us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5778.470s	38853.464us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	180.110s	3385.650us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	393.370s	4876.234us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2870.780s	18352.862us	1	1	100.00

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	chip_sival_flash_info_access	168.410s	2917.571us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	424.300s	5127.161us	1	1	100.00
	chip_sw_otp_ctrl_rot_auth_config	5.680s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	151.690s	3054.669us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	182.450s	2942.196us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	219.580s	4290.752us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	9.674s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	190.670s	3034.255us	1	1	100.00
	ate_bootstrap_flash_erase	6741.740s	44954.928us	1	1	100.00
	ate_bootstrap_disjoint	10065.470s	83851.767us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
	chip_sw_spi_device_pass_through_collision	112520827266718401286215975306209826712597753868531981375403178954464137751005	320	UVM_INFO @ 3955.355802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_flash_ctrl_lc_rw_en	56395749657734099173178460278148679557671443889148089534350279096980273434830	309	UVM_INFO @ 2918.032824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
	chip_sw_otp_ctrl_lc_signals_rma	95947881803562541621438541688234058034338693337858827890442626877837518003921	342	UVM_INFO @ 6584.608888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
	chip_sw_otp_ctrl_escalation	114356946043704014761345882094090697463194743678427357667670546309681843309249	316	UVM_ERROR @ 3454.559862 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3454.559862 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	95496319111845893814422193989438126416127445449722307012973904689424006733871	312	UVM_ERROR @ 3529.010718 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3529.010718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
	chip_sw_otp_ctrl_rot_auth_config	100689205051218884441495896581908129918285915055016245655606059588145349623500	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_lc_walkthrough_dev	84929668278113305667910317651996522916663631052674089211842033495207020436041	369	UVM_INFO @ 10012.582632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	47897063540517164258168591180460336106495270713243874563649064346540744850604	369	UVM_INFO @ 9557.566492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	91711539553669629406118130526977146952661470711713642051501831337131748188813	341	UVM_INFO @ 6491.498055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	113639753398884512479040785482315989217031996656198169001217163318103419001869	327	UVM_ERROR @ 9864.665500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 9864.665500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	22207346672022325124129446030166748271485994521062210589426665179518211120357	325	UVM_ERROR @ 7318.975000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7318.975000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	59015986904517171192672009576749964239633451370707645440520214614995194994478	319	UVM_ERROR @ 8316.832000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8316.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	63855718096152790978011705352712759045074239694991942829965895705532925991908	332	UVM_INFO @ 34591.427506 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert *!
	chip_sw_alert_test	34527210573668388417957122120032081207488788385423960451858500874330591971774	307	UVM_INFO @ 3312.951744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
	chip_sw_alert_handler_lpg_sleep_mode_alerts	65523526940461229980979439239688916166849216211799607258443794835937236404792	308	UVM_INFO @ 3382.365800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job killed!
	chip_sw_alert_handler_lpg_sleep_mode_pings	115452471279199110478023340614644571228339138643703561869115001105282696855869	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_clkmgr_jitter_frequency	76111885498223888812140156179493112027014537197169455931085064203113153449103	343	UVM_INFO @ 3220.315606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
	chip_sw_pwrmgr_sleep_wake_5_bug	39588103610589972781854497814029090634483959079664843972418663455193469093630	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	77611503074013309759726498573966517974306311464917645538611109443766945220683	None	Another command (pid=409603) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=398451) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=394783) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	103499975929366724090892318579437602813353229390515758975990529530831589144	None	Another command (pid=557425) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=577048) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=580742) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	39830877558280161417319217177793514960782020949426168065068436097695354537945	None	Another command (pid=560049) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=560562) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=566672) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	77485481193470455475207235272838305648519896320217063901287454850753750154054	None	Another command (pid=559234) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=553442) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=579838) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	90316078761843614234863597167681580217326929094523023438060735467798467736324	None	---- STDERR ---- Another command (pid=566672) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=570323) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	3864604220667328638009865885547967724998179995397468403092497567856220095028	None	Another command (pid=363265) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=409603) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=398451) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	68480099471984512378055611224635573749207223148245470441381078810671228412292	None	Another command (pid=436989) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=434563) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=548289) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	48025013898187974036283680504096013312022061284510832326716859530760857906374	None	Another command (pid=548289) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=480229) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=369837) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17436785893420833003838960186802492607861027570757282895230619951231304274420	None	Another command (pid=657447) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=781562) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=759096) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	4358248199723691338180018228879015069089447060771174833652294763585198145370	None	---- STDERR ---- Another command (pid=560049) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=560562) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	56725873346531540402761597496126400784967263641091655114242481840469491180854	None	Another command (pid=664314) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=615871) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=697281) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	100651207048520809112001573283515322396150961988519421467965476874980298118119	None	Another command (pid=588014) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=595768) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=600471) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	41073684655339302799533315850309661141762645137709398675609799865821427457703	None	Another command (pid=570323) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=558785) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=438157) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	91704574519343575398287082271725617275613189471022560070498621199155134023216	None	Another command (pid=697281) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=692956) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=694310) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	66191085511041946077505671290130830324272489888493043882106107875298957739593	None	Another command (pid=566672) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=568768) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=570323) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	81093677805773313967593950308990749245908214575680622327551569997123326886424	None	Another command (pid=613118) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=687495) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=690711) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	65568102120074930854136652673503868400191928984768112056884515113046714763299	None	Another command (pid=434563) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=548289) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=480229) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	79397021647085005882511194369896110363227338975368166859250291994348234323794	None	Another command (pid=597960) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=575224) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=461726) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	71672698316481722171615606642715502886351707807637669679713963466396573281935	None	Another command (pid=363265) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=409603) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=398451) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	16947447751755597268790765662811887040829377717561234861869530545920140730799	None	Another command (pid=437806) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=436989) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=434563) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	20928863381325706370236053773694080204324602432541017347288152053135663418594	None	Another command (pid=589840) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=564579) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=588014) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	4546071075931553066707879491425743459769294730557851502162406929977635236532	None	Another command (pid=409603) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=398451) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=418164) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	112473853397371180458532182741462134839966173351825234010761814759998295306338	None	Another command (pid=454546) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=558242) is running. Waiting for it to complete on the server (server_pid=245038)... Another command (pid=552004) is running. Waiting for it to complete on the server (server_pid=245038)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	88069642270689861585329313787796922831266477670598540995740156958794781042592	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	89703574629885085668684977360898173187527182004203395198505608559579203202469	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	102733341733421429347916276740277064806709910718984315824725899615170324450835	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	14991776971359829533866528780983457805538065527033080150006222918243271916370	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	9585070559327295611107505337164178930125928758296347097728083005652494545548	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	13225213245367640792720747989204446116233090178537087231227141990671577520244	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch
	chip_rv_dm_lc_disabled	89517279990014902111062072042725847598556120436443374291586501443295277134970	215	UVM_INFO @ 2080.840307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.
	chip_sw_rv_core_ibex_lockstep_glitch	861235486653269832805807890224073949706604053548516774127883077174817920054	323	UVM_INFO @ 2573.899735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
	chip_sw_power_idle_load	68903833664791450826036507024129345141589595350320787218515619717930673062374	312	UVM_INFO @ 2792.023500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
	chip_sw_power_sleep_load	40187040311622179957970308632254525173645591926647787632449488817518415835873	318	UVM_INFO @ 2715.580000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
	chip_sw_ast_clk_rst_inputs	37340397214095844647360050824677837912592335500823782012136450356616851486501	327	UVM_INFO @ 16100.426336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	28735231549548817128736490937742134256043971017410678711086127101020409650504	362	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	56443608103593942078340502696390976868087607517984600917814071694605345372990	325	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_dev	13386155879259042530453383748878680275367015448115420545440700850283487085584	368	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	13841305332737234727057263559837586586913167634269739002255205798014284102791	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_prod	67777567289256585851197367457617523202569294541305114855761636349098185438343	366	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	38610016643080020274500160368437075986379471649784975965100307276979925252907	365	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	94259686310299409157895291647369467722832790626178351541909045094675304319312	364	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	616937152971107663404369452608672188700425363131065473875781074559622307462	327	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26144102024409195546240521081611158702393566614615722770036748110602309520072	326	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	58653966285849887525821042508377652366388879432649603965484625452552739025621	326	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	38576414624019804861105735385773276607264062351002163301600465351074278244873	325	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	109421832023249424191751290643219467849026796420873328116527401653449373786724	325	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	45070115740231458498310022273693051791403418202867246148110043833384572447802	328	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	28165996615373565716365967235734743323791980644640598019561104506577064951653	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	89378516109400858324025994585673234077485267511962422844138521343248549864799	327	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
	rom_e2e_jtag_debug_dev	97777817324919887856036701428530307507661543196396371781650536982861639275272	330	UVM_INFO @ 14191.125841 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
	rom_e2e_keymgr_init_rom_ext_no_meas	3409820110602947317943103418619679217903706437718297938691121022632240429461	319	UVM_INFO @ 17074.559833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
	rom_keymgr_functest	77689742202641385159149625663881254955215648746380840112194119937738790870573	327	UVM_ERROR @ 4720.624440 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4720.624440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---