Simulation Results: clkmgr

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.96 %
  • code
  • 97.70 %
  • assert
  • 93.79 %
  • func
  • 84.39 %
  • line
  • 98.85 %
  • branch
  • 98.62 %
  • cond
  • 91.83 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.860s 64.165us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.770s 18.917us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.780s 15.206us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.520s 395.022us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.940s 37.749us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.570s 303.545us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.780s 15.206us 1 1 100.00
clkmgr_csr_aliasing 0.940s 37.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.990s 173.540us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.810s 19.002us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.870s 38.785us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.780s 43.518us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.860s 64.165us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.530s 358.188us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.550s 1342.717us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.530s 358.188us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 8.880s 2093.404us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.710s 33.833us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.720s 69.795us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.720s 69.795us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.770s 18.917us 1 1 100.00
clkmgr_csr_rw 0.780s 15.206us 1 1 100.00
clkmgr_csr_aliasing 0.940s 37.749us 1 1 100.00
clkmgr_same_csr_outstanding 1.050s 59.896us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.770s 18.917us 1 1 100.00
clkmgr_csr_rw 0.780s 15.206us 1 1 100.00
clkmgr_csr_aliasing 0.940s 37.749us 1 1 100.00
clkmgr_same_csr_outstanding 1.050s 59.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.810s 21.875us 0 1 0.00
clkmgr_tl_intg_err 1.660s 234.545us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.470s 152.153us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.470s 152.153us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.470s 152.153us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.470s 152.153us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.640s 102.951us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.660s 234.545us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.530s 358.188us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.550s 1342.717us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.470s 152.153us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.900s 39.353us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.780s 31.026us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.740s 46.396us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.930s 99.114us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.950s 52.115us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.780s 15.206us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.810s 21.875us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.780s 15.206us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.780s 15.206us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.810s 21.875us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.900s 1048.544us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 21.910s 5431.112us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 12719347010969566104266119028373797858590675097220129204050333387526925920849 96
UVM_INFO @ 21874862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---