Simulation Results: csrng

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.14 %
  • code
  • 92.78 %
  • assert
  • 92.58 %
  • func
  • 46.07 %
  • block
  • 95.30 %
  • line
  • 95.95 %
  • branch
  • 88.54 %
  • toggle
  • 91.41 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
83.33%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 107.390us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 17.291us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 33.131us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 185.864us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 101.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 33.506us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 33.131us 1 1 100.00
csrng_csr_aliasing 3.000s 101.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
alerts 1 1 100.00
csrng_alert 5.000s 158.809us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 333.183us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 333.183us 0 1 0.00
stress_all 0 1 0.00
csrng_stress_all 105.000s 4964.072us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 21.975us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 57.146us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 73.922us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 73.922us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.291us 1 1 100.00
csrng_csr_rw 2.000s 33.131us 1 1 100.00
csrng_csr_aliasing 3.000s 101.673us 1 1 100.00
csrng_same_csr_outstanding 4.000s 332.010us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 17.291us 1 1 100.00
csrng_csr_rw 2.000s 33.131us 1 1 100.00
csrng_csr_aliasing 3.000s 101.673us 1 1 100.00
csrng_same_csr_outstanding 4.000s 332.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
csrng_tl_intg_err 5.000s 180.153us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 1.000s 33.868us 1 1 100.00
csrng_csr_rw 2.000s 33.131us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 5.000s 158.809us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 105.000s 4964.072us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 5.000s 158.809us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 105.000s 4964.072us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 5.000s 158.809us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 180.153us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
csrng_sec_cm 3.000s 62.597us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 221.738us 1 1 100.00
csrng_err 2.000s 19.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 51661864781633572002849730755559579596177384022047655812599116248296612622160 130
UVM_INFO @ 333183410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 63971692985433708012859535022494344321257697251100945679715817007771076268765 144
UVM_INFO @ 4964072385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
csrng_stress_all_with_rand_reset 31602337914377246019165937324101785466811839910064098978959349353676887559980 None