Simulation Results: edn/edn0

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.45 %
  • code
  • 78.62 %
  • assert
  • 94.36 %
  • func
  • 77.38 %
  • line
  • 96.68 %
  • branch
  • 88.70 %
  • cond
  • 83.05 %
  • toggle
  • 73.58 %
  • FSM
  • 51.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 18.671us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 52.254us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 78.868us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.650s 132.189us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 53.584us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.980s 56.393us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 78.868us 1 1 100.00
edn_csr_aliasing 1.030s 53.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.030s 45.016us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.030s 45.016us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.030s 45.016us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.810s 41.918us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.990s 26.278us 1 1 100.00
errs 1 1 100.00
edn_err 0.820s 27.090us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 13.694us 1 1 100.00
edn_disable_auto_req_mode 1.010s 35.562us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.090s 307.487us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 31.131us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 52.249us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.020s 138.628us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.020s 138.628us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 52.254us 1 1 100.00
edn_csr_rw 0.750s 78.868us 1 1 100.00
edn_csr_aliasing 1.030s 53.584us 1 1 100.00
edn_same_csr_outstanding 1.080s 90.493us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 52.254us 1 1 100.00
edn_csr_rw 0.750s 78.868us 1 1 100.00
edn_csr_aliasing 1.030s 53.584us 1 1 100.00
edn_same_csr_outstanding 1.080s 90.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.840s 443.748us 1 1 100.00
edn_tl_intg_err 1.400s 48.319us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 23.347us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.990s 26.278us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.840s 443.748us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.840s 443.748us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.840s 443.748us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.840s 443.748us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.990s 26.278us 1 1 100.00
edn_sec_cm 3.840s 443.748us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.990s 26.278us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.400s 48.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 7.920s 429.398us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 34508155297651010907905811330718950235924331132948200438899690053386088800910 184
UVM_INFO @ 429397982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---