Simulation Results: edn/edn1

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.80 %
  • code
  • 82.80 %
  • assert
  • 97.14 %
  • func
  • 80.46 %
  • line
  • 98.18 %
  • branch
  • 93.07 %
  • cond
  • 88.15 %
  • toggle
  • 85.75 %
  • FSM
  • 48.86 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.970s 17.221us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.940s 15.937us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.720s 14.296us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.180s 217.466us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.110s 37.941us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.220s 28.233us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.720s 14.296us 1 1 100.00
edn_csr_aliasing 1.110s 37.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.080s 66.165us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.080s 66.165us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.080s 66.165us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 25.124us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 42.215us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 56.018us 1 1 100.00
disable 2 2 100.00
edn_disable 0.880s 23.160us 1 1 100.00
edn_disable_auto_req_mode 0.870s 90.660us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.200s 461.696us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 18.130us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 24.515us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.150s 46.022us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.150s 46.022us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.940s 15.937us 1 1 100.00
edn_csr_rw 0.720s 14.296us 1 1 100.00
edn_csr_aliasing 1.110s 37.941us 1 1 100.00
edn_same_csr_outstanding 0.800s 24.976us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.940s 15.937us 1 1 100.00
edn_csr_rw 0.720s 14.296us 1 1 100.00
edn_csr_aliasing 1.110s 37.941us 1 1 100.00
edn_same_csr_outstanding 0.800s 24.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.160s 385.231us 1 1 100.00
edn_tl_intg_err 1.300s 61.088us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.760s 56.260us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 42.215us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.160s 385.231us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.160s 385.231us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.160s 385.231us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.160s 385.231us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 42.215us 1 1 100.00
edn_sec_cm 4.160s 385.231us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 42.215us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.300s 61.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 21.360s 3172.869us 1 1 100.00