Simulation Results: flash_ctrl

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.32 %
  • code
  • 94.03 %
  • assert
  • 96.50 %
  • func
  • 95.42 %
  • line
  • 95.98 %
  • branch
  • 97.08 %
  • cond
  • 93.37 %
  • toggle
  • 98.01 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 63.910s 74.727us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.070s 52.074us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 14.240s 46.915us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.410s 204.861us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 40.760s 2535.225us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.510s 675.682us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 6.750s 38.427us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.410s 204.861us 1 1 100.00
flash_ctrl_csr_aliasing 22.510s 675.682us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.380s 19.710us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 9.380s 94.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.400s 147.909us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 49.280s 63.266us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1258.420s 334108.035us 1 1 100.00
flash_ctrl_hw_rma_reset 1093.860s 540321.969us 1 1 100.00
flash_ctrl_lcmgr_intg 5.660s 22.944us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1600.750s 289107.136us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 182.970s 1399.300us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 122.580s 9593.228us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 3124.940s 195640.638us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 40.550s 54.673us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.820s 42.627us 1 1 100.00
flash_ctrl_rw_evict_all_en 19.000s 115.775us 1 1 100.00
flash_ctrl_re_evict 18.480s 419.960us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 35.920s 195.063us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 35.920s 195.063us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 166.690s 78675.397us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.160s 1176.527us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 477.280s 409.880us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 524.940s 5077.183us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 373.830s 5546.835us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 946.990s 573.356us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.380s 42.566us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 136.420s 3732.182us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 12.540s 32.670us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.100s 31.321us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 352.360s 599.199us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 157.640s 2842.667us 1 1 100.00
flash_ctrl_otp_reset 58.840s 616.582us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1258.420s 334108.035us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 88.510s 772.684us 1 1 100.00
flash_ctrl_intr_wr 45.450s 7433.602us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 178.580s 12370.527us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 196.880s 101572.166us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 41.090s 1546.419us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.760s 678.645us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 12.270s 31.638us 1 1 100.00
flash_ctrl_ro_derr 94.740s 651.199us 1 1 100.00
flash_ctrl_rw_derr 148.720s 3253.020us 1 1 100.00
flash_ctrl_derr_detect 120.380s 3905.313us 1 1 100.00
flash_ctrl_integrity 437.770s 4175.816us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.570s 140.457us 1 1 100.00
flash_ctrl_ro_serr 84.960s 2887.085us 1 1 100.00
flash_ctrl_rw_serr 157.960s 6134.520us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 75.460s 1297.225us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 44.820s 705.155us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 102.530s 6590.886us 1 1 100.00
flash_ctrl_write_word_sweep 7.100s 135.284us 1 1 100.00
flash_ctrl_read_word_sweep 6.130s 26.860us 1 1 100.00
flash_ctrl_ro 83.970s 5012.108us 1 1 100.00
flash_ctrl_rw 378.280s 16549.587us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.150s 657.865us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 596.760s 40284.851us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 47.490s 10036.402us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.760s 73.229us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.930s 82.645us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.800s 35.935us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.800s 35.935us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.240s 46.915us 1 1 100.00
flash_ctrl_csr_rw 7.410s 204.861us 1 1 100.00
flash_ctrl_csr_aliasing 22.510s 675.682us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.850s 212.533us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 14.240s 46.915us 1 1 100.00
flash_ctrl_csr_rw 7.410s 204.861us 1 1 100.00
flash_ctrl_csr_aliasing 22.510s 675.682us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.850s 212.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 19.650s 88.267us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 19.650s 88.267us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 19.650s 88.267us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 19.650s 88.267us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 35.330s 1113.544us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
flash_ctrl_tl_intg_err 182.560s 1469.475us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 182.560s 1469.475us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 182.560s 1469.475us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.480s 63.699us 1 1 100.00
flash_ctrl_wr_intg 9.360s 159.691us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 63.910s 74.727us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 58.840s 616.582us 1 1 100.00
flash_ctrl_disable 12.540s 32.670us 1 1 100.00
flash_ctrl_sec_info_access 63.950s 22106.923us 1 1 100.00
flash_ctrl_connect 7.100s 31.321us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.620s 22.647us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.410s 204.861us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.650s 88.267us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.410s 204.861us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.650s 88.267us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.410s 204.861us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 19.650s 88.267us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 12.540s 32.670us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.480s 63.699us 1 1 100.00
flash_ctrl_access_after_disable 5.770s 44.353us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.970s 61.920us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 12.540s 32.670us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.160s 1176.527us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 378.280s 16549.587us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 157.960s 6134.520us 1 1 100.00
flash_ctrl_rw_derr 148.720s 3253.020us 1 1 100.00
flash_ctrl_integrity 437.770s 4175.816us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1258.420s 334108.035us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.370s 827.599us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 10.260s 177.503us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.800s 38.529us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1519.410s 1216.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.150s 68.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 163.140s 656.431us 1 1 100.00