Simulation Results: hmac

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.91 %
  • code
  • 97.94 %
  • assert
  • 96.70 %
  • func
  • 45.09 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.40 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 12.240s 3459.364us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.890s 46.150us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.900s 145.438us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.600s 2924.923us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.270s 105.152us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.890s 163.097us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.900s 145.438us 1 1 100.00
hmac_csr_aliasing 4.270s 105.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 33.500s 6753.188us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 57.190s 5921.942us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.550s 1405.665us 1 1 100.00
hmac_test_sha384_vectors 400.500s 12618.536us 1 1 100.00
hmac_test_sha512_vectors 20.730s 869.559us 1 1 100.00
hmac_test_hmac256_vectors 8.860s 552.240us 1 1 100.00
hmac_test_hmac384_vectors 11.040s 355.797us 1 1 100.00
hmac_test_hmac512_vectors 9.690s 872.414us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 11.090s 1543.733us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 755.890s 10387.894us 1 1 100.00
error 1 1 100.00
hmac_error 0.680s 44.444us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 2.650s 53.758us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 12.240s 3459.364us 1 1 100.00
hmac_long_msg 33.500s 6753.188us 1 1 100.00
hmac_back_pressure 57.190s 5921.942us 1 1 100.00
hmac_datapath_stress 755.890s 10387.894us 1 1 100.00
hmac_burst_wr 11.090s 1543.733us 1 1 100.00
hmac_stress_all 70.390s 20028.206us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 12.240s 3459.364us 1 1 100.00
hmac_long_msg 33.500s 6753.188us 1 1 100.00
hmac_back_pressure 57.190s 5921.942us 1 1 100.00
hmac_datapath_stress 755.890s 10387.894us 1 1 100.00
hmac_wipe_secret 2.650s 53.758us 1 1 100.00
hmac_test_sha256_vectors 8.550s 1405.665us 1 1 100.00
hmac_test_sha384_vectors 400.500s 12618.536us 1 1 100.00
hmac_test_sha512_vectors 20.730s 869.559us 1 1 100.00
hmac_test_hmac256_vectors 8.860s 552.240us 1 1 100.00
hmac_test_hmac384_vectors 11.040s 355.797us 1 1 100.00
hmac_test_hmac512_vectors 9.690s 872.414us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 12.240s 3459.364us 1 1 100.00
hmac_long_msg 33.500s 6753.188us 1 1 100.00
hmac_back_pressure 57.190s 5921.942us 1 1 100.00
hmac_datapath_stress 755.890s 10387.894us 1 1 100.00
hmac_burst_wr 11.090s 1543.733us 1 1 100.00
hmac_error 0.680s 44.444us 1 1 100.00
hmac_wipe_secret 2.650s 53.758us 1 1 100.00
hmac_test_sha256_vectors 8.550s 1405.665us 1 1 100.00
hmac_test_sha384_vectors 400.500s 12618.536us 1 1 100.00
hmac_test_sha512_vectors 20.730s 869.559us 1 1 100.00
hmac_test_hmac256_vectors 8.860s 552.240us 1 1 100.00
hmac_test_hmac384_vectors 11.040s 355.797us 1 1 100.00
hmac_test_hmac512_vectors 9.690s 872.414us 1 1 100.00
hmac_stress_all 70.390s 20028.206us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 70.390s 20028.206us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 66.847us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 13.477us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.930s 516.627us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.930s 516.627us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.890s 46.150us 1 1 100.00
hmac_csr_rw 0.900s 145.438us 1 1 100.00
hmac_csr_aliasing 4.270s 105.152us 1 1 100.00
hmac_same_csr_outstanding 1.020s 38.138us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.890s 46.150us 1 1 100.00
hmac_csr_rw 0.900s 145.438us 1 1 100.00
hmac_csr_aliasing 4.270s 105.152us 1 1 100.00
hmac_same_csr_outstanding 1.020s 38.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.970s 106.025us 1 1 100.00
hmac_tl_intg_err 3.800s 891.597us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.800s 891.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 12.240s 3459.364us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 726.863us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 66.880s 23638.146us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.230s 544.283us 1 1 100.00