Simulation Results

Simulation Results: i2c

15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.27 %

code
81.49 %

assert
95.56 %

func
78.75 %

line
96.41 %

branch
92.33 %

cond
85.23 %

toggle
89.45 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	62.130s	2387.006us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	15.040s	14697.941us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.790s	56.066us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.830s	99.734us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.360s	225.444us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.120s	27.763us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.390s	38.362us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.830s	99.734us	1	1	100.00
	i2c_csr_aliasing	1.120s	27.763us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.180s	346.886us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	268.550s	97983.004us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	622.630s	72797.383us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.780s	156.208us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	88.030s	25661.758us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	116.730s	2601.683us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.030s	119.319us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.500s	471.887us	1	1	100.00
	i2c_host_fifo_reset_rx	3.580s	584.401us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	131.710s	29779.064us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	27.130s	3377.622us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.430s	110.455us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.120s	1954.556us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	506.150s	41952.056us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.810s	7088.332us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	11.640s	1405.000us	1	1	100.00
	i2c_target_intr_smoke	2.730s	2831.328us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.240s	716.587us	1	1	100.00
	i2c_target_fifo_reset_tx	1.220s	235.143us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	357.640s	48756.777us	1	1	100.00
	i2c_target_stress_rd	11.640s	1405.000us	1	1	100.00
	i2c_target_intr_stress_wr	13.570s	2715.088us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.770s	3124.954us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	12.800s	2375.155us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.210s	1263.749us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	22.670s	10143.019us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.360s	338.242us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.360s	107.841us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	622.630s	72797.383us	1	1	100.00
	i2c_host_perf_precise	56.640s	23279.007us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	27.130s	3377.622us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.890s	144.969us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.100s	889.450us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.440s	448.587us	1	1	100.00
	i2c_target_nack_txstretch	1.380s	122.635us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.830s	1304.806us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.160s	3468.330us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.700s	16.263us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.810s	39.286us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.920s	109.222us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.920s	109.222us	1	1	100.00
tl_d_outstanding_access				3	4	75.00
	i2c_csr_hw_reset	0.790s	56.066us	1	1	100.00
	i2c_csr_rw	0.830s	99.734us	1	1	100.00
	i2c_csr_aliasing	1.120s	27.763us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	21.251us	0	1	0.00
tl_d_partial_access				3	4	75.00
	i2c_csr_hw_reset	0.790s	56.066us	1	1	100.00
	i2c_csr_rw	0.830s	99.734us	1	1	100.00
	i2c_csr_aliasing	1.120s	27.763us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	21.251us	0	1	0.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.080s	88.193us	1	1	100.00
	i2c_sec_cm	1.430s	432.935us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.080s	88.193us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	3.790s	304.095us	1
target_error_intr				1
	i2c_target_unexp_stop	1.450s	180.696us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	28.030s	2064.282us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	63540144259359684324088872667211838810418320584967673119868554555177283074893	110	UVM_INFO @ 346885582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	111859633220707133991265835743095917847639292300119298084166184834871331028688	84	UVM_INFO @ 1954556357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	67160800693445074014830008726688223716477993275284357809322869576962313611953	78	UVM_INFO @ 180695589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	79979207017663189741095653396771307090929084162440088435228999470543900559632	79	UVM_INFO @ 10143019440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	10870132284610428864843413142543974324622780156208148091294121270061634469837	84	UVM_INFO @ 304094964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	55078145810971208567110716496371143818869742656152784748785235744208565059492	100	UVM_INFO @ 2064281527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
	i2c_host_mode_toggle	93626466952131503581808730594596858398127697149910854633690336631107920199645	87	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------
UVM_ERROR (cip_base_vseq.sv:847) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [] vs [*])
	i2c_same_csr_outstanding	33336106197029732614083532299454209373596842209280262945999306493969791972492	77	UVM_INFO @ 21250643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---