Simulation Results: kmac/unmasked

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.00 %
  • code
  • 87.89 %
  • assert
  • 97.75 %
  • func
  • 93.36 %
  • line
  • 97.27 %
  • branch
  • 95.36 %
  • cond
  • 94.07 %
  • toggle
  • 99.87 %
  • FSM
  • 52.89 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 8.650s 1589.756us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.090s 38.870us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.270s 41.708us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 15.070s 5983.429us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.450s 746.966us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.680s 190.261us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.270s 41.708us 1 1 100.00
kmac_csr_aliasing 5.450s 746.966us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.870s 11.484us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.790s 91.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 316.390s 5268.810us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 218.820s 12536.190us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1221.920s 17304.629us 1 1 100.00
kmac_test_vectors_sha3_256 27.470s 2086.481us 1 1 100.00
kmac_test_vectors_sha3_384 15.590s 437.148us 1 1 100.00
kmac_test_vectors_sha3_512 10.950s 277.464us 1 1 100.00
kmac_test_vectors_shake_128 145.190s 38223.802us 1 1 100.00
kmac_test_vectors_shake_256 73.260s 1617.491us 1 1 100.00
kmac_test_vectors_kmac 2.510s 151.462us 1 1 100.00
kmac_test_vectors_kmac_xof 2.040s 109.801us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 232.930s 30605.013us 1 1 100.00
app 1 1 100.00
kmac_app 22.530s 1086.147us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 104.470s 27973.438us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 60.930s 6095.751us 1 1 100.00
error 1 1 100.00
kmac_error 338.920s 94398.806us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 5.270s 2349.098us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 90.680s 10022.831us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 7.930s 1251.814us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 12.860s 1127.565us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 12.750s 6265.104us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.630s 42.937us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 143.150s 2410.053us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.700s 47.060us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.040s 15.380us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.690s 451.728us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.690s 451.728us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.090s 38.870us 1 1 100.00
kmac_csr_rw 1.270s 41.708us 1 1 100.00
kmac_csr_aliasing 5.450s 746.966us 1 1 100.00
kmac_same_csr_outstanding 2.120s 95.032us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.090s 38.870us 1 1 100.00
kmac_csr_rw 1.270s 41.708us 1 1 100.00
kmac_csr_aliasing 5.450s 746.966us 1 1 100.00
kmac_same_csr_outstanding 2.120s 95.032us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.100s 47.622us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.100s 47.622us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.100s 47.622us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.100s 47.622us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.140s 311.344us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 17.390s 6462.040us 1 1 100.00
kmac_tl_intg_err 4.570s 109.381us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.570s 109.381us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.630s 42.937us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 8.650s 1589.756us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 232.930s 30605.013us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.100s 47.622us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 17.390s 6462.040us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 17.390s 6462.040us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 17.390s 6462.040us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 8.650s 1589.756us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.630s 42.937us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 17.390s 6462.040us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 194.200s 8895.315us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 8.650s 1589.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 111.490s 9916.190us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 98978567722721037092952367111815153974961392173141638466843777245923798331294 79
UVM_INFO @ 10022831208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---