Simulation Results: lc_ctrl/volatile_unlock_disabled

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.65 %
  • code
  • 84.41 %
  • assert
  • 94.13 %
  • func
  • 93.42 %
  • line
  • 97.26 %
  • branch
  • 93.97 %
  • cond
  • 79.59 %
  • toggle
  • 87.68 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.420s 22.882us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.340s 23.265us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.980s 237.297us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.190s 276.463us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 34.822us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.410s 92.686us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.980s 237.297us 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 34.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.200s 81.627us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.590s 1822.060us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.040s 40.135us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.200s 424.016us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.260s 369.218us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_prog_failure 2.200s 424.016us 1 1 100.00
lc_ctrl_errors 8.260s 369.218us 1 1 100.00
lc_ctrl_security_escalation 5.520s 965.181us 1 1 100.00
lc_ctrl_jtag_state_failure 25.820s 7366.697us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.810s 305.482us 1 1 100.00
lc_ctrl_jtag_errors 17.780s 6764.368us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.440s 1040.772us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.640s 2525.495us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.810s 305.482us 1 1 100.00
lc_ctrl_jtag_errors 17.780s 6764.368us 1 1 100.00
lc_ctrl_jtag_access 2.310s 300.588us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.930s 3933.715us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.510s 227.769us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.100s 56.334us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.890s 342.771us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.260s 1604.356us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.320s 53.567us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.590s 246.418us 1 1 100.00
lc_ctrl_jtag_alert_test 1.440s 99.731us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.920s 3340.026us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 27.013us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 73.880s 7094.894us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.080s 127.842us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.070s 251.975us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.070s 251.975us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 23.265us 1 1 100.00
lc_ctrl_csr_rw 0.980s 237.297us 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 34.822us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.920s 147.879us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 23.265us 1 1 100.00
lc_ctrl_csr_rw 0.980s 237.297us 1 1 100.00
lc_ctrl_csr_aliasing 1.670s 34.822us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.920s 147.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
lc_ctrl_tl_intg_err 1.590s 212.437us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.590s 212.437us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.590s 1822.060us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.680s 492.423us 1 1 100.00
lc_ctrl_sec_cm 8.190s 251.168us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.520s 965.181us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.200s 81.627us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.640s 2525.495us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.610s 1180.114us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.610s 1180.114us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.500s 750.618us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.490s 1177.209us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.490s 1177.209us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 13.240s 2163.010us 1 1 100.00