Simulation Results: lc_ctrl/volatile_unlock_enabled

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.92 %
  • code
  • 83.83 %
  • assert
  • 94.13 %
  • func
  • 91.81 %
  • line
  • 97.06 %
  • branch
  • 93.47 %
  • cond
  • 79.14 %
  • toggle
  • 88.71 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.290s 26.783us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.970s 66.218us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.880s 64.613us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.010s 37.996us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 91.534us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.250s 48.537us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.880s 64.613us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 91.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.560s 103.737us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.250s 834.643us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 42.756us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.440s 21.889us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.590s 537.212us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_prog_failure 1.440s 21.889us 1 1 100.00
lc_ctrl_errors 7.590s 537.212us 1 1 100.00
lc_ctrl_security_escalation 3.950s 764.609us 1 1 100.00
lc_ctrl_jtag_state_failure 37.460s 41807.607us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.500s 288.793us 1 1 100.00
lc_ctrl_jtag_errors 37.650s 4591.090us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.980s 291.265us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.000s 3615.902us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.500s 288.793us 1 1 100.00
lc_ctrl_jtag_errors 37.650s 4591.090us 1 1 100.00
lc_ctrl_jtag_access 4.330s 428.893us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.550s 2597.837us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.040s 73.441us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.970s 35.144us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 27.210s 3289.939us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.530s 1339.785us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.190s 29.162us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.590s 429.776us 1 1 100.00
lc_ctrl_jtag_alert_test 1.250s 81.249us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.570s 3024.217us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.270s 14.261us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 22.390s 1753.332us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 65.059us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.870s 295.680us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.870s 295.680us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 66.218us 1 1 100.00
lc_ctrl_csr_rw 0.880s 64.613us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 91.534us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 127.385us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.970s 66.218us 1 1 100.00
lc_ctrl_csr_rw 0.880s 64.613us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 91.534us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 127.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 118.298us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.770s 118.298us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.250s 834.643us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.290s 1163.513us 1 1 100.00
lc_ctrl_sec_cm 6.240s 230.961us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.950s 764.609us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.560s 103.737us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.000s 3615.902us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.670s 261.672us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.670s 261.672us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.410s 419.815us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.860s 426.468us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.860s 426.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 37.060s 3607.307us 1 1 100.00