Simulation Results: otbn

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.21 %
  • code
  • 95.26 %
  • assert
  • 89.50 %
  • func
  • 97.88 %
  • block
  • 99.35 %
  • line
  • 99.55 %
  • branch
  • 91.88 %
  • toggle
  • 92.18 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 43.294us 1 1 100.00
single_binary 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 28.000s 21.947us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 23.000s 25.342us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 27.000s 208.991us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 26.000s 38.580us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 25.000s 174.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 23.000s 25.342us 1 1 100.00
otbn_csr_aliasing 26.000s 38.580us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 59.000s 8277.876us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 46.000s 1600.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 24.000s 291.004us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 47.000s 327.277us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 55.000s 837.215us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 105.000s 362.330us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 12.152us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 89.220us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 96.561us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 26.000s 26.941us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 56.677us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 195.581us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 195.581us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 28.000s 21.947us 1 1 100.00
otbn_csr_rw 23.000s 25.342us 1 1 100.00
otbn_csr_aliasing 26.000s 38.580us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.396us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 28.000s 21.947us 1 1 100.00
otbn_csr_rw 23.000s 25.342us 1 1 100.00
otbn_csr_aliasing 26.000s 38.580us 1 1 100.00
otbn_same_csr_outstanding 4.000s 18.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 45.050us 1 1 100.00
otbn_dmem_err 21.000s 23.119us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 32.000s 34.350us 1 1 100.00
otbn_controller_ispr_rdata_err 34.000s 41.260us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 73.778us 1 1 100.00
otbn_urnd_err 4.000s 29.074us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.694us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 12.743us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 10.478us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
otbn_tl_intg_err 18.000s 338.576us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 47.000s 222.349us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 43.294us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 21.000s 23.119us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 45.050us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 338.576us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 12.152us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 45.050us 1 1 100.00
otbn_dmem_err 21.000s 23.119us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 89.220us 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.694us 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 45.050us 1 1 100.00
otbn_dmem_err 21.000s 23.119us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 89.220us 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.694us 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 12.152us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 45.050us 1 1 100.00
otbn_dmem_err 21.000s 23.119us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 89.220us 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.694us 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 27.000s 30.257us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 24.692us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 79.000s 961.709us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 79.000s 961.709us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 38.350us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 16.000s 111.327us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 17.988us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 17.988us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 49.834us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 55.000s 837.215us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 20.000s 61.919us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 36.000s 113.207us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 194.000s 4604.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 30.000s 270.134us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 22.117us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 89280647861585647510488776301131406420956461868074416153114940849966262300385 233
UVM_INFO @ 270134115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---