Simulation Results: pattgen

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
81.82%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 234.967us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 59.597us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 16.348us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 77.383us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 17.538us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 24.499us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 16.348us 1 1 100.00
pattgen_csr_aliasing 1.000s 17.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 2088.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 2.000s 32.413us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 186.622us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 3.000s 346.637us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 20.905us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 182.426us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 81.630us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 81.630us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 59.597us 1 1 100.00
pattgen_csr_rw 1.000s 16.348us 1 1 100.00
pattgen_csr_aliasing 1.000s 17.538us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 90.083us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 59.597us 1 1 100.00
pattgen_csr_rw 1.000s 16.348us 1 1 100.00
pattgen_csr_aliasing 1.000s 17.538us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 90.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_tl_intg_err 2.000s 463.972us 1 1 100.00
pattgen_sec_cm 2.000s 308.005us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 463.972us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 16.000s 4826.675us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 196.000s 10086.803us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 9231679812617845189744421285441387548673320405172036414102366712556252999388 99
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
pattgen_inactive_level 29273806370015621885819006322780109531630920927838775275138123395288829332856 99
UVM_INFO @ 10086802832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 49037762617166352139324640905275852448112585369587793402351047797065252342320 124
UVM_ERROR @ 1786609314 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1786609314 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1786669314 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:
pattgen_stress_all 69542360516508478312122495375442225638821909183778076248437911258602554188257 153
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @10080