Simulation Results: pwrmgr

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 94.52 %
  • assert
  • 96.34 %
  • func
  • 96.54 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 94.06 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.700s 34.829us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 48.717us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.620s 19.664us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.470s 320.428us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.090s 157.122us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.810s 43.751us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.620s 19.664us 1 1 100.00
pwrmgr_csr_aliasing 1.090s 157.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.770s 112.857us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.770s 112.857us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.920s 55.698us 1 1 100.00
pwrmgr_lowpower_invalid 0.690s 82.610us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.920s 72.085us 1 1 100.00
pwrmgr_reset_invalid 0.800s 163.269us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.920s 72.085us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.660s 48.525us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.680s 236.394us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.680s 113.068us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 18.420s 10921.574us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.680s 30.097us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.990s 519.989us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.990s 519.989us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 48.717us 1 1 100.00
pwrmgr_csr_rw 0.620s 19.664us 1 1 100.00
pwrmgr_csr_aliasing 1.090s 157.122us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 41.675us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 48.717us 1 1 100.00
pwrmgr_csr_rw 0.620s 19.664us 1 1 100.00
pwrmgr_csr_aliasing 1.090s 157.122us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 41.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.620s 9.384us 0 1 0.00
pwrmgr_sec_cm 0.760s 35.616us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.760s 35.616us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.760s 35.616us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.620s 9.384us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.420s 1103.386us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.660s 48.525us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.740s 57.363us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.690s 30.659us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.760s 35.616us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.760s 35.616us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.760s 35.616us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.640s 49.610us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.780s 62.547us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.040s 223.534us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 19.664us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 19.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 1.000s 183.298us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.700s 3435.240us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 84579512678710904142438257301042171688121522563818246695278801449790219125146 79
UVM_ERROR @ 183298210 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 183298210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 25811397804268356053715647964351837232982024306505419525797201206810906454231 85
UVM_INFO @ 9383573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 14702680228903396108283066789269745976325457942704342998359925369414803955 85
UVM_INFO @ 35615791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
pwrmgr_stress_all 96484323146114940136862537688668573848406681884377368531852585976414350230457 519
UVM_INFO @ 10921573943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---