Simulation Results: rom_ctrl/32kb

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.37 %
  • code
  • 97.93 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.59 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 99.97 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.300s 135.602us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.860s 435.398us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.110s 175.884us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.310s 166.948us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.800s 602.727us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.210s 313.043us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.110s 175.884us 1 1 100.00
rom_ctrl_csr_aliasing 3.800s 602.727us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.540s 126.276us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.400s 537.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.220s 227.777us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.000s 751.395us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.250s 2426.174us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.720s 289.091us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.090s 202.357us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.090s 202.357us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.860s 435.398us 1 1 100.00
rom_ctrl_csr_rw 4.110s 175.884us 1 1 100.00
rom_ctrl_csr_aliasing 3.800s 602.727us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.580s 133.118us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.860s 435.398us 1 1 100.00
rom_ctrl_csr_rw 4.110s 175.884us 1 1 100.00
rom_ctrl_csr_aliasing 3.800s 602.727us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.580s 133.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.630s 403.099us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 94.480s 1019.421us 1 1 100.00
rom_ctrl_tl_intg_err 41.110s 2194.202us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 94.480s 1019.421us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 94.480s 1019.421us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 94.480s 1019.421us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 94.480s 1019.421us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.300s 135.602us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.300s 135.602us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.300s 135.602us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.110s 2194.202us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
rom_ctrl_kmac_err_chk 6.250s 2426.174us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 54.900s 1490.891us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.630s 403.099us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 94.480s 1019.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 430.610s 19143.395us 1 1 100.00