Simulation Results: rom_ctrl/64kb

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.37 %
  • code
  • 97.94 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.62 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.720s 1042.179us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.530s 1099.426us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.350s 291.459us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.140s 215.636us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.740s 376.342us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.960s 1082.443us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.350s 291.459us 1 1 100.00
rom_ctrl_csr_aliasing 5.740s 376.342us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.600s 677.348us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.760s 1310.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.170s 300.096us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 22.330s 10893.213us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.940s 1040.752us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.730s 545.610us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.660s 1115.243us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.660s 1115.243us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.530s 1099.426us 1 1 100.00
rom_ctrl_csr_rw 7.350s 291.459us 1 1 100.00
rom_ctrl_csr_aliasing 5.740s 376.342us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.220s 1066.086us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.530s 1099.426us 1 1 100.00
rom_ctrl_csr_rw 7.350s 291.459us 1 1 100.00
rom_ctrl_csr_aliasing 5.740s 376.342us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.220s 1066.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 54.110s 6316.288us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 445.490s 2225.674us 1 1 100.00
rom_ctrl_tl_intg_err 49.680s 1028.480us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 445.490s 2225.674us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 445.490s 2225.674us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 445.490s 2225.674us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 445.490s 2225.674us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.720s 1042.179us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.720s 1042.179us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.720s 1042.179us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 49.680s 1028.480us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
rom_ctrl_kmac_err_chk 14.940s 1040.752us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 165.350s 5177.730us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 54.110s 6316.288us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 445.490s 2225.674us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 63.410s 16373.622us 1 1 100.00