Simulation Results: rstmgr

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.07 %
  • code
  • 99.09 %
  • assert
  • 97.86 %
  • func
  • 97.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 97.92 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.240s 199.873us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.060s 93.940us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.810s 75.189us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.640s 2017.955us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.150s 357.784us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.410s 183.331us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.810s 75.189us 1 1 100.00
rstmgr_csr_aliasing 2.150s 357.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.730s 89.999us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.640s 359.877us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.990s 131.320us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.620s 1444.337us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.620s 1444.337us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.620s 1444.337us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.620s 1444.337us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 14.010s 4465.766us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.940s 90.495us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.400s 207.195us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.400s 207.195us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.060s 93.940us 1 1 100.00
rstmgr_csr_rw 0.810s 75.189us 1 1 100.00
rstmgr_csr_aliasing 2.150s 357.784us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 125.368us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.060s 93.940us 1 1 100.00
rstmgr_csr_rw 0.810s 75.189us 1 1 100.00
rstmgr_csr_aliasing 2.150s 357.784us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 125.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 40.640s 31362.826us 1 1 100.00
rstmgr_tl_intg_err 1.660s 458.663us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 40.640s 31362.826us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 40.640s 31362.826us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.660s 458.663us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.880s 111.785us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.250s 2255.253us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.540s 301.785us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 40.640s 31362.826us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 75.189us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 75.189us 1 1 100.00