Simulation Results: rv_timer

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.16 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 97.65 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.610s 1153.716us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.850s 14.815us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.690s 12.585us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.450s 398.196us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.830s 23.671us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.020s 19.940us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.690s 12.585us 1 1 100.00
rv_timer_csr_aliasing 0.830s 23.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.800s 1834.188us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.880s 827.741us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 18.780s 20370.923us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 18.780s 20370.923us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.580s 4957.723us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 44.153us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 11.504us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.320s 400.285us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.320s 400.285us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.850s 14.815us 1 1 100.00
rv_timer_csr_rw 0.690s 12.585us 1 1 100.00
rv_timer_csr_aliasing 0.830s 23.671us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 67.945us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.850s 14.815us 1 1 100.00
rv_timer_csr_rw 0.690s 12.585us 1 1 100.00
rv_timer_csr_aliasing 0.830s 23.671us 1 1 100.00
rv_timer_same_csr_outstanding 0.630s 67.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.160s 356.732us 1 1 100.00
rv_timer_tl_intg_err 1.320s 252.337us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.320s 252.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.610s 14.103us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.840s 223.726us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 21.660s 14788.165us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*])
rv_timer_max 86023327463703643702899293438906013920811809593816188234597779051103261588931 75
UVM_INFO @ 223725541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 101844455848637573871635922647694419097049791356777739677638341293708423571637 75
UVM_INFO @ 1834188472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---