Simulation Results: spi_device/1r1w

 
15/04/2026 16:33:45 DVSim: v1.30.1 sha: cf700e4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.03 %
  • code
  • 93.24 %
  • assert
  • 94.64 %
  • func
  • 61.21 %
  • line
  • 99.02 %
  • branch
  • 98.16 %
  • cond
  • 96.13 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 44.140s 23432.223us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.130s 59.388us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.960s 95.288us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.950s 3603.769us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.250s 11376.301us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.660s 214.736us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.960s 95.288us 1 1 100.00
spi_device_csr_aliasing 15.250s 11376.301us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 14.975us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.830s 28.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.810s 16.376us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.790s 5.799us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.860s 3.538us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.120s 158.694us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.120s 158.694us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 17.290s 9551.916us 1 1 100.00
spi_device_tpm_sts_read 0.890s 39.342us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 5.840s 784.124us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.790s 975.537us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.510s 140.301us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.510s 140.301us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.190s 971.965us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.190s 971.965us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.190s 971.965us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.190s 971.965us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.190s 971.965us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.680s 2754.030us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 2.330s 147.196us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 2.330s 147.196us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 2.330s 147.196us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.560s 355.282us 1 1 100.00
spi_device_read_buffer_direct 3.290s 224.525us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 2.330s 147.196us 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 4.160s 296.147us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.940s 1328.101us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.940s 1328.101us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 44.140s 23432.223us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 11.240s 3735.053us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 8.710s 1113.087us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.800s 13.127us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.910s 253.079us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.370s 846.700us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.370s 846.700us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.130s 59.388us 1 1 100.00
spi_device_csr_rw 1.960s 95.288us 1 1 100.00
spi_device_csr_aliasing 15.250s 11376.301us 1 1 100.00
spi_device_same_csr_outstanding 1.490s 364.054us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.130s 59.388us 1 1 100.00
spi_device_csr_rw 1.960s 95.288us 1 1 100.00
spi_device_csr_aliasing 15.250s 11376.301us 1 1 100.00
spi_device_same_csr_outstanding 1.490s 364.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.380s 207.039us 1 1 100.00
spi_device_tl_intg_err 9.290s 194.641us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.290s 194.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 201.420s 176940.820us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 83823200515053023098854140132257579574687256521310810028409873504721105248057 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3799188 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3799188 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[988])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 39076236768269022398666118297054991237504477244013839077973299347788923302324 76
UVM_ERROR @ 1215968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2b2984 [1010110010100110000100] vs 0x0 [0])
UVM_ERROR @ 1222968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8b9c40 [100010111001110001000000] vs 0x0 [0])
UVM_ERROR @ 1239968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd8f96d [110110001111100101101101] vs 0x0 [0])
UVM_ERROR @ 1300968 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5b9b06 [10110111001101100000110] vs 0x0 [0])